Lines Matching full:phy

4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
13   "#phy-cells":
15     description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19       - lantiq,vrx200-pcie-phy
20       - lantiq,arx300-pcie-phy
27       - description: PHY module clock
32       - const: phy
37       - description: exclusive PHY reset line
38       - description: shared reset line between the PCIe PHY and PCIe controller
42       - const: phy
51     description: the offset of the endian registers for this PHY instance in the RCU syscon
55     description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
58     description: Configures the PDI (PHY) registers in big-endian mode
62     description: Configures the PDI (PHY) registers in big-endian mode
66   - "#phy-cells"
81     pcie0_phy: phy@106800 {
82         compatible = "lantiq,vrx200-pcie-phy";
89         clock-names = "phy", "pdi";
91         reset-names = "phy", "pcie";
92         #phy-cells = <1>;