Lines Matching +full:0 +full:xf

32 		pinctrl-single,power-source = <0x30 0xf0>;
38 		pinctrl-single,bias-pullup = <0 1 0 1>;
44 		pinctrl-single,bias-pulldown = <2 2 0 2>;
61 		pinctrl-single,input-schmitt = <0x30 0x70>;
67 		pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
74 		pinctrl-single,low-power-mode = <0x288 0x388>;
83 		pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
102 	pinctrl-single,pins = <0xdc 0x118>;
104 Where 0xdc is the offset from the pinctrl register base address for the device
105 pinctrl register, and 0x118 contains the desired value of the pinctrl register.
109 	pinctrl-single,pins = <0xdc 0x30 0x07>;
111 Where 0x30 is the pin configuration value and 0x07 is the pin mux mode value.
112 These two values are OR'd together to produce the value stored at offset 0xdc.
118 	pinctrl-single,bits = <0xdc 0x18 0xff>;
120 Where 0xdc is the offset from the pinctrl register base address for the
121 device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
145 	reg = <0x4a100040 0x0196>;
147 	#size-cells = <0>;
151 	pinctrl-single,function-mask = <0xffff>;
157 	reg = <0x4a31e040 0x0038>;
159 	#size-cells = <0>;
163 	pinctrl-single,function-mask = <0xffff>;
168 	reg = <0x48002274 4>;	/* Single register */
170 	#size-cells = <0>;
173 	pinctrl-single,function-mask = <0x5F>;
179 	reg = <0xd401e000 0x0330>;
188 	pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
189 				&range 12 1 0 &range 13 29 1
190 				&range 43 1 0 &range 44 49 1
208 	pinctrl-0 = <&board_pins>;
212 			0x6c 0xf
213 			0x6e 0xf
214 			0x70 0xf
215 			0x72 0xf
221 			0x208 0		/* UART0_RXD (IOCFG138) */
222 			0x20c 0		/* UART0_TXD (IOCFG139) */
224 		pinctrl-single,bias-pulldown = <0 2 2>;
225 		pinctrl-single,bias-pullup = <0 1 1>;
231 			0xd8 0x118
232 			0xda 0
233 			0xdc 0x118
234 			0xde 0
242 			0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
248 			0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
256        pinctrl-0 = <&uart0_pins>;
261        pinctrl-0 = <&uart2_pins>;