Lines Matching +full:- +full:pins
10 GMII_RXD3 ---+
12 DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)
14 BGPIO16 ---+ ^
26 KEY_ROW2 ---+ v
27 PORT1_LCD_TE ---+ |
28 | AGPIO10 ---+------ KEY_ROW2 (AON pin)
29 I2S0_DOUT3 ---+ |
30 |-----------------------+
31 PWM_OUT3 ---+
33 VGA_VS1 ---+
36 For most of pins like GMII_RXD3 in the figure, the pinmux function is
37 controlled by TOP_PMM block only, and this type of pins are meant by term
38 'TOP pins'. For pins like KEY_ROW2, the pinmux is controlled by both
40 the pin spread in both controllers. This type of pins are called 'AON pins'.
42 types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG
46 - compatible: should be "zte,zx296718-pmm".
47 - reg: the register physical address and length.
48 - zte,auxiliary-controller: phandle to the auxiliary pin controller which
49 implements pinmux for AON pins and pinconf for all pins.
52 pinctrl-bindings.txt in this directory for more details of the common
55 - bias-pull-up
56 - bias-pull-down
57 - drive-strength
58 - input-enable
59 - slew-rate
63 iocfg: pin-controller@119000 {
64 compatible = "zte,zx296718-iocfg";
68 pmm: pin-controller@1462000 {
69 compatible = "zte,zx296718-pmm";
71 zte,auxiliary-controller = <&iocfg>;
76 pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2";
82 pinctrl-names = "default";
83 pinctrl-0 = <&vga_pins>;