Lines Matching +full:0 +full:x8
17 - #address-cells: should be 0
18 - #size-cells: should be 0
32 0-bypass
56 from efuse-address to pick up ABB characteristics. Set to 0 if
60 + efuse maps to RBB mask. Set to 0 to ignore this.
64 Set to 0 to ignore this.
72 #address-cells = <0>;
73 #size-cells = <0>;
74 reg = <0x483072f0 0x8>, <0x48306818 0x4>;
76 ti,tranxdone-status-mask = <0x4000000>;
82 1012500 0 0 0 0 0 /* Bypass */
83 1200000 3 0 0 0 0 /* RBB mandatory */
84 1320000 1 0 0 0 0 /* FBB mandatory */
92 #address-cells = <0>;
93 #size-cells = <0>;
94 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, <0x4A002268 0x8>;
96 ti,tranxdone-status-mask = <0x4000000>;
102 975000 0 0 0 0 0 /* Bypass */
103 1012500 0 0 0x40000 0 0 /* RBB optional */
104 1200000 0 0x4 0 0x40000 0 /* FBB optional */
105 1320000 1 0 0 0 0 /* FBB mandatory */
113 #address-cells = <0>;
114 #size-cells = <0>;
115 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
116 <0x4a002194 0x8>, <0x4ae0C314 0x4>;
119 ti,tranxdone-status-mask = <0x8000000>;
121 ti,ldovbb-override-mask = <0x400>;
123 ti,ldovbb-vset-mask = <0x1F>;
129 975000 0 0 0 0 0 /* Bypass */
130 1200000 0 0x4 0 0x40000 0x1f00 /* FBB optional, vset */