Lines Matching +full:memory +full:- +full:region
1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
18 L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
29 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
34 - ti,j721e-c66-dsp
35 - ti,j721e-c71-dsp
37 Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs
38 Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs
46 firmware-name:
53 OMAP Mailbox specifier denoting the sub-mailbox, to be used for
55 with the sub-mailbox node used in the firmware image.
58 memory-region:
62 phandle to the reserved memory nodes to be associated with the remoteproc
63 device. There should be at least two reserved memory nodes defined. The
64 reserved memory nodes should be carveout nodes, and should be defined as
66 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
68 - description: region used for dynamic DMA allocations like vrings and
70 - description: region reserved for firmware image sections
74 # --------------------
77 $ref: /schemas/types.yaml#/definitions/phandle-array
81 phandles to one or more reserved on-chip SRAM regions. The regions
90 - ti,j721e-c66-dsp
95 - description: Address and Size of the L2 SRAM internal memory region
96 - description: Address and Size of the L1 PRAM internal memory region
97 - description: Address and Size of the L1 DRAM internal memory region
98 reg-names:
100 - const: l2sram
101 - const: l1pram
102 - const: l1dram
108 - ti,j721e-c71-dsp
113 - description: Address and Size of the L2 SRAM internal memory region
114 - description: Address and Size of the L1 DRAM internal memory region
115 reg-names:
117 - const: l2sram
118 - const: l1dram
121 - compatible
122 - reg
123 - reg-names
124 - ti,sci
125 - ti,sci-dev-id
126 - ti,sci-proc-ids
127 - resets
128 - firmware-name
129 - mboxes
130 - memory-region
135 - |
139 #address-cells = <2>;
140 #size-cells = <2>;
143 compatible = "simple-bus";
144 #address-cells = <2>;
145 #size-cells = <2>;
153 compatible = "ti,j721e-c66-dsp";
157 reg-names = "l2sram", "l1pram", "l1dram";
159 ti,sci-dev-id = <142>;
160 ti,sci-proc-ids = <0x03 0xFF>;
162 firmware-name = "j7-c66_0-fw";
163 memory-region = <&c66_0_dma_memory_region>,
170 compatible = "ti,j721e-c71-dsp";
173 reg-names = "l2sram", "l1dram";
175 ti,sci-dev-id = <15>;
176 ti,sci-proc-ids = <0x30 0xFF>;
178 firmware-name = "j7-c71_0-fw";
179 memory-region = <&c71_0_dma_memory_region>,