Lines Matching +full:reg +full:- +full:shift
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: /schemas/serial.yaml#
14 - if:
16 - aspeed,sirq-polarity-sense
20 const: aspeed,ast2500-vuart
21 - if:
24 const: mrvl,mmp-uart
27 reg-shift:
30 - reg-shift
31 - if:
36 - enum:
37 - ns8250
38 - ns16450
39 - ns16550
40 - ns16550a
43 - required: [ clock-frequency ]
44 - required: [ clocks ]
49 - const: ns8250
50 - const: ns16450
51 - const: ns16550
52 - const: ns16550a
53 - const: ns16850
54 - const: aspeed,ast2400-vuart
55 - const: aspeed,ast2500-vuart
56 - const: intel,xscale-uart
57 - const: mrvl,pxa-uart
58 - const: nuvoton,npcm750-uart
59 - const: nvidia,tegra20-uart
60 - const: nxp,lpc3220-uart
61 - items:
62 - enum:
63 - altr,16550-FIFO32
64 - altr,16550-FIFO64
65 - altr,16550-FIFO128
66 - fsl,16550-FIFO64
67 - fsl,ns16550
68 - andestech,uart16550
69 - nxp,lpc1850-uart
70 - opencores,uart16550-rtlsvn105
71 - ti,da830-uart
72 - const: ns16550a
73 - items:
74 - enum:
75 - ns16750
76 - cavium,octeon-3860-uart
77 - xlnx,xps-uart16550-2.00.b
78 - ralink,rt2880-uart
79 - enum:
80 - ns16550 # Deprecated, unless the FIFO really is broken
81 - ns16550a
82 - items:
83 - enum:
84 - ralink,mt7620a-uart
85 - ralink,rt3052-uart
86 - ralink,rt3883-uart
87 - const: ralink,rt2880-uart
88 - enum:
89 - ns16550 # Deprecated, unless the FIFO really is broken
90 - ns16550a
91 - items:
92 - enum:
93 - mediatek,mt7622-btif
94 - mediatek,mt7623-btif
95 - const: mediatek,mtk-btif
96 - items:
97 - const: mrvl,mmp-uart
98 - const: intel,xscale-uart
99 - items:
100 - enum:
101 - nvidia,tegra30-uart
102 - nvidia,tegra114-uart
103 - nvidia,tegra124-uart
104 - nvidia,tegra186-uart
105 - nvidia,tegra194-uart
106 - nvidia,tegra210-uart
107 - const: nvidia,tegra20-uart
109 reg:
115 clock-frequency: true
123 current-speed:
127 reg-offset:
131 reg-shift:
132 description: Quantity to shift the register offsets by.
134 reg-io-width:
137 device. There are some systems that require 32-bit accesses to the
140 used-by-rtas:
146 no-loopback-test:
151 fifo-size:
155 auto-flow-control:
162 tx-threshold:
168 overrun-throttle-ms:
172 rts-gpios: true
173 cts-gpios: true
174 dtr-gpios: true
175 dsr-gpios: true
176 rng-gpios: true
177 dcd-gpios: true
179 aspeed,sirq-polarity-sense:
180 $ref: /schemas/types.yaml#/definitions/phandle-array
182 Phandle to aspeed,ast2500-scu compatible syscon alongside register
185 applicable to aspeed,ast2500-vuart.
188 - reg
189 - interrupts
194 - |
197 reg = <0x80230000 0x100>;
199 reg-shift = <2>;
200 clock-frequency = <48000000>;
202 - |
203 #include <dt-bindings/gpio/gpio.h>
206 reg = <0x49042000 0x400>;
208 clock-frequency = <48000000>;
209 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
210 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
211 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
212 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
213 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
214 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
216 - |
217 #include <dt-bindings/clock/aspeed-clock.h>
219 compatible = "aspeed,ast2500-vuart";
220 reg = <0x1e787000 0x40>;
221 reg-shift = <2>;
224 no-loopback-test;
225 aspeed,sirq-polarity-sense = <&syscon 0x70 25>;