Lines Matching +full:assigned +full:- +full:clock +full:- +full:parents

4 - compatible: should be one of the following.
5     - mediatek,mt2712-spi-slave: for mt2712 platforms
6 - reg: Address and length of the register set for the device.
7 - interrupts: Should contain spi interrupt.
8 - clocks: phandles to input clocks.
9   It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>.
10 - clock-names: should be "spi" for the clock gate.
13 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
14 - assigned-clock-parents: parent of mux clock.
16    -  <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
18    -  <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
19    -  <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
20    -  <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
23 - SoC Specific Portion:
25 	compatible = "mediatek,mt2712-spi-slave";
29 	clock-names = "spi";
30 	assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
31 	assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;