Lines Matching +full:0 +full:x09
23 ivtvctl -O min=0x02000000,max=0x020000ff
32 (Base Address Register 0). The addresses here are offsets relative to the
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
44 0x01000000-0x01ffffff Decoder memory space
45 0x01000000-0x0103ffff Decode.rom
47 0x0114b000-0x0115afff Audio.rom (deprecated?)
49 0x02000000-0x0200ffff Register Space
54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
59 DMA Registers 0x000-0xff:
61 0x00 - Control:
62 0=reset/cancel, 1=read, 2=write, 4=stop
63 0x04 - DMA status:
65 0x08 - pci DMA pointer for read link list
66 0x0c - pci DMA pointer for write link list
67 0x10 - read/write DMA enable:
69 0x14 - always 0xffffffff, if set any lower instability occurs, 0x00 crashes
70 0x18 - ??
71 0x1c - always 0x20 or 32, smaller values slow down DMA transactions
72 0x20 - always value of 0x780a010a
73 0x24-0x3c - usually just random values???
74 0x40 - Interrupt status
75 0x44 - Write a bit here and shows up in Interrupt status 0x40
76 0x48 - Interrupt Mask
77 0x4C - always value of 0xfffdffff,
78 if changed to 0xffffffff DMA write interrupts break.
79 0x50 - always 0xffffffff
80 0x54 - always 0xffffffff (0x4c, 0x50, 0x54 seem like interrupt masks, are
83 0x60-0x7C - random values
84 0x80 - first write linked list reg, for Encoder Memory addr
85 0x84 - first write linked list reg, for pci memory addr
86 0x88 - first write linked list reg, for length of buffer in memory addr
87 (|0x80000000 or this for last link)
88 0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
89 from linked list addr in reg 0x0c, firmware must push through or
91 0xe0 - first (and only) read linked list reg, for pci memory addr
92 0xe4 - first (and only) read linked list reg, for Decoder memory addr
93 0xe8 - first (and only) read linked list reg, for length of buffer
94 0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.
96 Memory locations for Encoder Buffers 0x700-0x7ff:
101 - 0x07F8: Encoder SDRAM refresh
102 - 0x07FC: Encoder SDRAM pre-charge
104 Memory locations for Decoder Buffers 0x800-0x8ff:
109 - 0x08F8: Decoder SDRAM refresh
110 - 0x08FC: Decoder SDRAM pre-charge
114 - 0x2800: Video Display Module control
115 - 0x2D00: AO (audio output?) control
116 - 0x2D24: Bytes Flushed
117 - 0x7000: LSB I2C write clock bit (inverted)
118 - 0x7004: LSB I2C write data bit (inverted)
119 - 0x7008: LSB I2C read clock bit
120 - 0x700c: LSB I2C read data bit
121 - 0x9008: GPIO get input state
122 - 0x900c: GPIO set output state
123 - 0x9020: GPIO direction (Bit7 (GPIO 0..7) - 0:input, 1:output)
124 - 0x9050: SPU control
125 - 0x9054: Reset HW blocks
126 - 0x9058: VPU control
127 - 0xA018: Bit6: interrupt pending?
128 - 0xA064: APU command
134 The definition of the bits in the interrupt status register 0x0040, and the
135 interrupt mask 0x0048. If a bit is cleared in the mask, then we want our ISR to
171 - The 1st 32-bit word of the Encoder image is 0x0000da7
172 - The 1st 32-bit word of the Decoder image is 0x00003a7
173 - The 2nd 32-bit word of both images is 0xaa55bb66
187 - Write 0x00000000 to register 0x2800 to stop the Video Display Module.
188 - Write 0x00000005 to register 0x2D00 to stop the AO (audio output?).
189 - Write 0x00000000 to register 0xA064 to ping? the APU.
190 - Write 0xFFFFFFFE to register 0x9058 to stop the VPU.
191 - Write 0xFFFFFFFF to register 0x9054 to reset the HW blocks.
192 - Write 0x00000001 to register 0x9050 to stop the SPU.
194 - Write 0x0000001A to register 0x07FC to init the Encoder SDRAM's pre-charge.
195 - Write 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.
196 - Write 0x0000001A to register 0x08FC to init the Decoder SDRAM's pre-charge.
197 - Write 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.
199 - Transfer the encoder's firmware image to offset 0 in Encoder memory space.
200 - Transfer the decoder's firmware image to offset 0 in Decoder memory space.
201 - Use a read-modify-write operation to Clear bit 0 of register 0x9050 to
204 - Use a read-modify-write operation to Clear bits 3 and 0 of register 0x9058
223 0x78, 0x56, 0x34, 0x12, 0x12, 0x78, 0x56, 0x34,
224 0x34, 0x12, 0x78, 0x56, 0x56, 0x34, 0x12, 0x78
233 0 Flags
249 0 I Driver is using this mailbox.
257 - 0=success
269 first one available (bit 0 has been cleared). The driver sets that bit, fills
295 Enum: 65/0x41
302 Result[0]
317 Enum: 66/0x42
324 Result[0]
327 0=8bit index
338 Enum: 67/0x43
345 Param[0]
348 - 0=8bit index
359 Enum: 68/0x44
366 Result[0]
369 - Bit 0 0=off, 1=on
378 Enum: 69/0x45
385 Param[0]
388 0=off, 1=on
395 Enum: 70/0x46
402 Result[0]
432 Enum: 71/0x47
439 Param[0]
469 Enum: 72/0x48
476 Result[0]
501 Enum: 73/0x49
508 Param[0]
533 Enum: 74/0x4A
540 Result[0]
543 global alpha: 0=off, 1=on
548 bits 0:7 global alpha
555 Enum: 75/0x4B
562 Param[0]
565 global alpha: 0=off, 1=on
575 local alpha: 0=on, 1=off
582 Enum: 78/0x4C
589 Param[0]
604 Enum: 79/0x4F
611 Result[0]
614 flicker state: 0=off, 1=on
621 Enum: 80/0x50
628 Param[0]
631 State: 0=off, 1=on
638 Enum: 82/0x52
645 Param[0]
685 '01' if source_alpha=0:
691 '10' if destination_alpha=0:
693 if 255 > destination_alpha > 0:
697 '11' if source_alpha=0:
698 source_temp = 0
701 if 255 > source_alpha > 0:
703 if destination_alpha=0:
704 destination_temp = 0
707 if 255 > destination_alpha > 0:
751 Enum: 83/0x53
758 Param[0]
761 Same as Param[0] on API 0x52
766 Same as Param[1] on API 0x52
771 Same as Param[2] on API 0x52
808 Enum: 84/0x54
815 Param[0]
818 Same as Param[0] on API 0x52
823 Same as Param[1] on API 0x52
828 Same as Param[2] on API 0x52
875 Enum: 86/0x56
883 Param[0]
908 Enum: 96/0x60
915 Param[0]
918 state: 0=off, 1=on
930 Enum: 97/0x61
937 Result[0]
940 alpha content index, Range 0:15
947 Enum: 98/0x62
954 Param[0]
957 alpha content index, range 0:15
966 Enum: 128/0x80
978 Enum: 129/0x81
987 Param[0]
992 - 0=MPEG
1003 - Bit 0 when set, captures YUV
1005 - Bit 2 when set, captures VBI (same as param[0]=3)
1007 (same as param[0]=2)
1017 Enum: 130/0x82
1024 Param[0]
1027 - 0=stop at end of GOP (generates IRQ)
1033 Stream type to stop, see param[0] of API 0x81
1038 Subtype, see param[1] of API 0x81
1045 Enum: 137/0x89
1052 Param[0]
1062 Enum: 139/0x8B
1069 Param[0]
1079 Enum: 141/0x8D
1086 Param[0]
1096 Enum: 143/0x8F
1103 Param[0]
1106 - 0=30fps
1114 Enum: 145/0x91
1121 Param[0]
1136 Enum: 149/0x95
1143 Param[0]
1146 0=variable bitrate, 1=constant bitrate
1161 Mux bitrate in bits per second, divided by 400. May be 0 (default).
1175 #) Param\[3\] and Param\[4\] seem to be always 0
1183 Enum: 151/0x97
1190 Param[0]
1210 Enum: 153/0x99
1218 Param[0]
1233 Enum: 155/0x9B
1240 Param[0]
1251 - 0=Disabled
1262 Enum: 157/0x9D
1268 the respective filter is set to "manual" (See API 0x9B)
1270 Param[0]
1273 Spatial filter: default 0, range 0:15
1278 Temporal filter: default 0, range 0:31
1285 Enum: 159/0x9F
1292 Param[0]
1296 Default: 0, range 0:255
1302 Default: 255, range 0:255
1308 Default: 0, range 0:255
1314 Default: 255, range 0:255
1321 Enum: 161/0xA1
1328 Param[0]
1333 - 0=Off
1344 - 0=Off
1352 Enum: 183/0xB7
1359 Param[0]
1362 - Bits 0:4 line number
1363 - Bit 31 0=top_field, 1=bottom_field
1364 - Bits 0:31 all set specifies "all lines"
1369 VBI line information features: 0=disabled, 1=enabled
1374 Slicing: 0=None, 1=Closed Caption
1375 Almost certainly not implemented. Set to 0.
1381 Almost certainly not implemented. Set to 0.
1387 Almost certainly not implemented. Set to 0.
1394 Enum: 185/0xB9
1407 Param[0]
1410 - 0=Program stream
1427 Enum: 187/0xBB
1432 Assign stream output port. Normally 0 when the data is copied through
1436 Param[0]
1439 - 0=Memory (default)
1446 Unknown, but leaving this to 0 seems to work best. Indications are that
1447 this might have to do with USB support, although passing anything but 0
1455 Enum: 189/0xBD
1476 Param[0]
1483 0:1 '00' 44.1Khz
1540 '0' off
1544 '0' off
1548 '0' copy
1556 Enum: 195/0xC3
1569 Enum: 196/0xC4
1576 Result[0]
1580 - Bits 0:15 build
1589 Enum: 197/0xC5
1596 Param[0]
1599 - 0=Open
1607 Enum: 198/0xC6
1614 which will have Result[0] set to 1 and Result[1] will contain the size
1617 Result[0]
1625 If Result[0] is 1, this contains the size of the last buffer, undefined
1633 Enum: 199/0xC7
1647 u32 mask1; // Bits 0-2 are the type mask:
1649 // 0=End of Program Index, other fields
1652 u32 mask2; // Bit 0 is bit 32 of the pts.
1662 Param[0]
1666 - 0=No index capture
1678 Result[0]
1693 Enum: 200/0xC8
1700 Param[0]
1707 0 Mode '0' Sliced, '1' Raw
1713 8:15 Stream ID (normally 0xBD)
1745 Result[0]
1765 Enum: 201/0xC9
1772 Param[0]
1781 Unit: 0=bytes, 1=frames
1788 Enum: 202/0xCA
1796 Result[0]
1816 Enum: 203/0xCB
1824 Result[0]
1828 - 0 read completed
1842 Presentation Time Stamp bits 0..31
1854 Enum: 204/0xCC
1861 Param[0]
1874 DMA type (0=MPEG)
1881 Enum: 205/0xCD
1893 Enum: 208/0xD0
1900 Param[0]
1910 Enum: 210/0xD2
1917 Param[0]
1920 - 0=Pause encoding
1928 Enum: 211/0xD3
1940 Enum: 212/0xD4
1947 Param[0]
1951 - 0=Stream is not copyrighted
1959 Enum: 213/0xD5
1967 Param[0]
1970 Event (0=refresh encoder input)
1975 Notification 0=disabled 1=enabled
1992 Enum: 214/0xD6
2000 Param[0]
2004 - 0x00EF for SAA7114
2005 - 0x00F0 for SAA7115
2006 - 0x0105 for Micronas
2012 - 0x00EF for SAA7114
2013 - 0x00F0 for SAA7115
2014 - 0x0106 for Micronas
2021 Enum: 215/0xD7
2028 Param[0]
2031 - 0=extension & user data
2032 - 1=private packet with stream ID 0xBD
2048 Custom data 0
2095 Enum: 217/0xD9
2102 Param[0]
2109 0 '0'=video not muted
2121 Enum: 218/0xDA
2128 Param[0]
2131 - 0=audio not muted
2139 Enum: 219/0xDB
2146 Param[0]
2150 Else 0.
2157 Enum: 220/0xDC
2166 Param[0]
2176 Always 1 for the cx23416 and 0 for cx23415.
2180 7=set navigation pack insertion for DVD: adds 0xbf (private stream 2)
2182 the header of 6 bytes: 0x000001bf + length). The payload is zeroed and
2211 Enum: 0/0x00
2224 Enum: 1/0x01
2231 Param[0]
2234 0 based frame number in GOP to begin playback from.
2240 audio resumes. (This is not implemented in the firmware, leave at 0)
2247 Enum: 2/0x02
2255 Param[0]
2258 Display 0=last frame, 1=black
2263 then use '0', otherwise the screen goes to black at once.
2282 Enum: 3/0x03
2295 Param[0]
2301 0:7 0 normal
2305 '0' during 1.5 times play, every other B frame is dropped
2309 '0' slow
2320 Direction: 0=forward, 1=reverse
2351 Mute audio: 0=disable, 1=enable
2356 Display 0=frame, 1=field
2362 resumes. (Not implemented in the firmware, leave at 0)
2369 Enum: 5/0x05
2377 Param[0]
2380 0=frame, 1=top field, 2=bottom field
2387 Enum: 8/0x08
2392 Set DMA transfer block size. Counterpart to API 0xC9
2394 Param[0]
2405 Enum: 9/0x09
2412 Result[0]
2437 Enum: 10/0x0A
2444 Result[0]
2454 DMA type: 0=MPEG, 1=OSD, 2=YUV
2461 Enum: 11/0x0B
2466 Setup DMA from host operation. Counterpart to API 0xCC
2468 Param[0]
2481 DMA type (0=MPEG, 1=OSD, 2=YUV)
2488 Enum: 13/0x0D
2497 Param[0]
2500 Display: 0=last frame, 1=black
2507 Enum: 14/0x0E
2520 Enum: 16/0x10
2527 Param[0]
2530 0=NTSC, 1=PAL
2537 Enum: 17/0x11
2544 Result[0]
2548 - Bits 0:15 build
2557 Enum: 20/0x14
2564 Param[0]
2567 0=memory (default), 1=streaming
2574 Enum: 21/0x15
2581 Result[0]
2589 Video PTS bits 0:31 by display order
2599 SCR bits 0:31 by display order
2611 Enum: 22/0x16
2618 Param[0]
2622 0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged
2628 0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged
2635 Enum: 23/0x17
2641 Counterpart to API 0xD5
2643 Param[0]
2647 - 0=Audio mode change between mono, (joint) stereo and dual channel.
2655 Notification 0=disabled, 1=enabled
2672 Enum: 24/0x18
2680 Param[0]
2683 0=six buffers, 1=nine buffers
2690 Enum: 25/0x19
2697 Param[0]
2700 0=extract from extension & user data, 1=extract from private packets
2702 Result[0]
2717 Enum: 26/0x1A
2725 Param[0]
2728 Mode: 0=MPEG from host, 1=YUV from encoder, 2=YUV from host
2743 Bitmap: see Param[0] of API 0xBD
2750 Enum: 30/0x1E
2758 Param[0]
2761 0=off, 1=on
2763 PVR350 Video decoder registers 0x02002800 -> 0x02002B00
2783 is required. For registers containing size information, setting them to 0 is
2791 bit 0
2793 0 = disable
2797 bits 0:31
2801 bits 0:31
2805 bits 0:31
2809 bits 0:31
2813 bits 0:31
2817 bits 0:31
2831 bits 0:31
2835 bits 0:31
2839 bits 0:31
2843 bits 0:31
2847 bits 0:31
2851 bits 0:31
2860 bits 0:15
2867 bits 0:15
2880 bits 0:31
2885 bits 0:31
2887 Usually 0x00080514
2890 bits 0:31
2895 bits 0:31
2897 Usually 0x00100514
2900 bits 0:31
2902 Usually 0x00200020
2905 bits 0:31
2907 Usually 0x00200020
2910 bits 0:31
2914 bits 0:31
2916 Usually 0
2919 bits 0:31
2924 bits 0:31
2926 Usually 0
2929 bits 0:31
2934 bits 0:31
2936 Usually 0
2944 Reg 2854 = (source_width * 0x00200000) / destination_width
2948 Reg 2854 = (source_width/2 * 0x00200000) / destination width
2952 Reg 2854 = (source_width/4 * 0x00200000) / destination width
2959 bits 0:15
2970 bits 0:15
2982 bits 0:1
2996 0 = Normal
3001 0 = Normal
3006 bit 0
3011 0 = osd off
3016 0 = NTSC
3028 bits 0:10
3030 Moves entire screen horizontally. Starts at 0x005 with the screen
3031 shifted heavily to the right. Incrementing in steps of 0x004 will
3037 Normally contents are 0x00101111 (NTSC) or 0x1010111d (PAL)
3044 bit 0
3046 0 = Normal
3056 Known to be bad are 0x000,0x011,0x100,0x111
3059 bits 0:15
3066 Same as bits 0:15
3070 bits 0:11
3081 bits 0:23
3088 bits 0:23
3095 0 = Video on
3100 0 = Y,UV
3105 0 = Normal (UV)
3115 bits 0:15
3122 the image on screen. Known starting values are 0x011E0017 (NTSC) &
3123 0x01500017 (PAL)
3126 bits 0:15
3137 bits 0:11
3140 Has a range of 0x770->0x7FF. With the exception of 0, any value outside of
3144 bits 0:15
3151 the image on screen. Known starting values are 0x011E0017 (NTSC) &
3152 0x01500017 (PAL)
3160 bit 0
3162 0 = first field
3176 bit 0
3178 0 = Normal
3182 bits 0:31
3186 bits 0:31
3190 bits 0:31
3201 bits 0:31
3205 bits 0:31
3209 bits 0:31
3216 bits 0:15
3223 bits 0:15
3236 bits 0:31
3241 bits 0:31
3243 Normally = Reg 2920 + 0x514
3246 bits 0:31
3252 bits 0:31
3254 Normally = Reg 2928 + 0x514
3257 bits 0:31
3261 bits 0:31
3265 bits 0:31
3270 bits 0:31
3274 bits 0:31
3280 bits 0:31
3284 bits 0:31
3289 bits 0:31
3298 Reg 2930 = (source_height * 0x00200000) / destination_height
3302 Reg 2930 = (source_height/2 * 0x00200000) / destination height
3306 Reg 2930 = (source_height/4 * 0x00200000) / destination height
3311 bits 0:15
3318 bits 0:15
3325 bits 0:15
3332 bits 0:15
3339 bits 0:15
3346 bits 0:15
3356 bits 0:15
3366 bits 0:1
3379 bit 0
3381 0 = Normal
3386 0 = Normal
3396 bits 0:2
3412 0 = Off
3417 0 = Off
3422 0 = Off
3431 0 = ARGB
3436 Must be 0x001B (some kind of buffer pointer ?)
3451 bit indexed, local alpha is a per-pixel 256 step transparency, with 0 being
3453 bit(s) act as a simple transparency switch, with 0 being solid & 1 being
3457 with 0 being transparent & 255 being solid.
3462 bits 0:15
3469 bits 0:15
3475 For both registers, (0,0) = top left corner of the display area. These
3482 bits 0:31
3489 bits 0:11
3496 bits 0:15
3504 bits 0:31
3510 bits 0:7
3521 bits 0:7
3525 bits 0:31
3530 so the index range is 0x00-0xFF
3536 bits 0:31
3542 bits 0:31
3548 bits 0:31
3554 bits 0:31
3560 bits 0:31
3566 bits 0:31
3577 bit 0
3579 0 = filter off
3641 - Results[0]: Type: 0: MPEG.
3679 Register 0x0004 holds the DMA Transfer Status:
3681 - bit 0: read completed