Lines Matching full:features

22 device MMIO space to provide an extensible way of adding features. Software can
23 walk through these predefined data structures to enumerate FPGA features:
24 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
62 Private Features represent sub features of the FIU and AFU. They could be
63 various function blocks with different IDs, but all private features which
72 This Device Feature List provides a way of linking features together, it's
133 to the accelerator and exposes features such as reset and debug. Each FPGA
201 (FPGA base region), discover feature devices and their private features from the
204 also abstracts operations for the private features and exposes common ops to
216 provides the key features for FPGA management, including:
258 Features supported by the particular FPGA device are exposed through Device
473 Some FME and AFU private features are able to generate interrupts. As mentioned
480 In Current DFL, 3 sub features (Port error, FME global error and AFU interrupt)
494 Add new private features support
496 In some cases, we may need to add some new private features to existing FIUs