Lines Matching +full:0 +full:x2a
40 pair is located at the HWM Base Address + 0 and the HWM Base Address + 1. The
41 HWM Base address can be obtained from Logical Device 8, registers 0x60 (MSB)
42 and 0x61 (LSB). Currently we are using 0x480 for the HWM Base Address and
43 0x480 and 0x481 for the index/data pair.
49 Temp1 0x25 (Currently, this reflects the CPU temp on all systems).
50 Temp2 0x26
51 Temp3 0x27
52 Temp4 0x80
67 Ex: If AL contains 0x2A, the temperature is 42 degrees C.
74 Tach1 0x28 0x29 (Currently, this reflects the CPU
76 Tach2 0x2A 0x2B
77 Tach3 0x2C 0x2D
78 Tach4 0x2E 0x2F
95 Reg 0x28 = 0x9B
96 Reg 0x29 = 0x08
98 TCount = 0x89B = 2203
115 To place the chip into the Configuration State The config key (0x55) is written
116 to the CONFIG PORT (0x2E).
127 (i.e., 0x07) to the INDEX PORT and then write the number of the
140 To exit the Configuration State the write 0xAA to the CONFIG PORT (0x2E).
146 The following is an example of how to read the SIO Device ID located at 0x20:
161 MOV AX,0AAH
165 (0x20) and Device Rev (0x21).
167 The Device ID will read 0x6F (0x81 for SCH5307-NS, and 0x85 for SCH5317)
168 The Device Rev currently reads 0x01
196 MOV AX,0AAH