Lines Matching +full:tx +full:- +full:queues +full:- +full:to +full:- +full:use
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
17 These are SPI-managed automotive switches, with all ports being gigabit
21 set-and-forget use, with minimal dynamic interaction at runtime. They
22 require a static configuration to be composed by software and packed
56 Also the configuration is write-only (software cannot read it back from the
60 all times in memory, as a shadow for the hardware state. When required to
62 If that changed setting can be transmitted to the switch through the dynamic
71 programmable filters for link-local destination MACs.
72 These are used to trap BPDUs and PTP traffic to the master netdevice, and are
73 further used to support STP and 1588 ordinary clock/boundary clock
74 functionality. For frames trapped to the CPU, source port and switch ID
77 But by leveraging ``CONFIG_NET_DSA_TAG_8021Q`` (a software-defined DSA tagging
78 format based on VLANs), general-purpose traffic termination through the network
84 - Mode 1 (VLAN-unaware): a port is in this mode when it is used as a standalone
85 net device, or when it is enslaved to a bridge with ``vlan_filtering=0``.
86 - Mode 2 (fully VLAN-aware): a port is in this mode when it is enslaved to a
87 bridge with ``vlan_filtering=1``. Access to the entire VLAN range is given to
88 the user through ``bridge vlan`` commands, but general-purpose (anything
91 through the DSA master interface (similar to ``DSA_TAG_PROTO_NONE``).
92 - Mode 3 (best-effort VLAN-aware): a port is in this mode when enslaved to a
94 switch named ``best_effort_vlan_filtering`` is set to ``true``. When
95 configured like this, the range of usable VIDs is reduced (0 to 1023 and 3072
96 to 4094), so is the number of usable VIDs (maximum of 7 non-pvid VLANs per
100 To summarize, in each mode, the following types of traffic are supported over
103 +-------------+-----------+--------------+------------+
107 | traffic | | (use master) | |
108 +-------------+-----------+--------------+------------+
112 +-------------+-----------+--------------+------------+
114 To configure the switch to operate in Mode 3, the following steps can be
120 # swp2 temporarily moves to Mode 2
128 # Cannot use VLANs in range 1024-3071 while in Mode 3.
152 # Cannot use mode than 7 VLANs per port while in Mode 3.
155 \* "maximum of 7 non-pvid VLANs per port": Decoding VLAN-tagged packets on the
157 switch to the CPU. In cross-chip topologies, the port that goes to the CPU
158 might also go to other switches. In that case, those other switches will see
160 interested in this VLAN, they need to apply retagging in the reverse direction,
161 to recover the original value from it. This consumes extra hardware resources
165 As an example, consider this cross-chip topology::
167 +-------------------------------------------------+
169 | +-------------------------+ |
171 | | switch (non-sja1105) | |
172 | +--------+-------------------------+--------+ |
175 | | +--------------+ +--------------+ | |
178 +--+---+--------------+-----+--------------+---+--+
180 +-----------------------+ +-----------------------+
182 +-----+-----+-----+-----+ +-----+-----+-----+-----+
184 +-----+-----+-----+-----+ +-----+-----+-----+-----+
186 To reach the CPU, SJA1105 switch 1 (spi/spi2.1) uses the same port as is uses
187 to reach SJA1105 switch 2 (spi/spi2.2), which would be port 4 (not drawn).
190 Also consider the following commands, that add VLAN 100 to every sja1105 user
238 towards the CPU. It also consumes 1 retagging entry for each non-pvid VLAN that
245 - 8 retagging entries for VLANs 1 and 100 installed on its user ports
246 (``sw1p0`` - ``sw1p3``)
247 - 3 retagging entries for VLAN 100 installed on the user ports of SJA1105
248 switch 2 (``sw2p0`` - ``sw2p2``), because it also has ports that are
254 - 7 retagging entries for the bridge VLANs on its user ports (``sw2p0`` -
256 - 4 retagging entries for VLAN 100 installed on the user ports of SJA1105
257 switch 1 (``sw1p0`` - ``sw1p3``).
269 The hardware tags all traffic internally with a port-based VLAN (pvid), or it
273 This behavior is available when switch ports are enslaved to a bridge with
276 Normally the hardware is not configurable with respect to VLAN awareness, but
285 ``vlan_filtering`` enslaves at least one switch port, the other un-bridged
299 The switch ports (swp0-3) are under br0.
301 with swp0-3.
303 If br0 has vlan_filtering 0, then eth0 can simply be added to br0 with the
305 If br0 has vlan_filtering 1, then a new br1 interface needs to be created that
313 Time-aware scheduling
314 ---------------------
317 specified in IEEE 802.1Q-2018 (formerly 802.1Qbv). This means it can be used to
318 ensure deterministic latency for priority traffic that is sent in-band with its
319 gate-open event in the network schedule.
321 This capability can be managed through the tc-taprio offload ('flags 2'). The
322 difference compared to the software implementation of taprio is that the latter
323 would only be able to shape traffic originated from the CPU, but not
326 The device has 8 traffic classes, and maps incoming frames to one of them based
327 on the VLAN PCP bits (if no VLAN is present, the port-based default is used).
333 EtherType. In these modes, injecting into a particular TX queue can only be
336 offloaded flows can be steered to TX queues based on the VLAN PCP, but the DSA
337 net devices are no longer able to do that. To inject frames into a hardware TX
338 queue with VLAN awareness active, it is necessary to create a VLAN
339 sub-interface on the DSA master port, and send normal (0x8100) VLAN-tagged
342 Management traffic (having DMAC 01-80-C2-xx-xx-xx or 01-19-1B-xx-xx-xx) is the
354 set -e -u -o pipefail
369 if ! systemctl is-active --quiet ptp4l; then
375 # Phase-align the base time to the start of the next second.
376 sec=$(echo "${now}" | gawk -F. '{ print $1; }')
382 queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \
383 base-time ${base_time} \
384 sched-entry S $(gatemask 7) 100000 \
385 sched-entry S $(gatemask "0 1 2 3 4 5 6") 400000 \
388 It is possible to apply the tc-taprio offload on multiple egress ports. There
389 are hardware restrictions related to the fact that no gate event may trigger
392 needed to avoid this, which is outside the scope of the document.
395 --------------------------------------
397 The switch is able to offload flow-based redirection of packets to a set of
399 making use of Virtual Links, a TTEthernet concept.
403 - VLAN-aware virtual links: these match on destination MAC address, VLAN ID and
405 - VLAN-unaware virtual links: these match on destination MAC address only.
411 actions are requested, the driver creates a "non-critical" virtual link. When
412 the action list also contains tc-gate (more details below), the virtual link
413 becomes "time-critical" (draws frame buffers from a reserved memory partition,
418 Example 1: send frames received on swp2 with a DA of 42:be:24:9b:76:20 to the
419 CPU and to swp3. This type of key (DA only) when the port's VLAN awareness
433 Time-based ingress policing
434 ---------------------------
436 The TTEthernet hardware abilities of the switch can be constrained to act
437 similarly to the Per-Stream Filtering and Policing (PSFP) clause specified in
438 IEEE 802.1Q-2018 (formerly 802.1Qci). This means it can be used to perform
439 tight timing-based admission control for up to 1024 flows (identified by a
443 This capability can be managed through the offload of the tc-gate action. As
444 routing actions are intrinsic to virtual links in TTEthernet (which performs
445 explicit routing of time-critical traffic and does not leave that in the hands
446 of the FDB, flooding etc), the tc-gate action may never appear alone when
447 asking sja1105 to offload it. One (or more) redirect or trap actions must also
450 Example: create a tc-taprio schedule that is phase-aligned with a tc-gate
454 (and much more so, in this example) to compensate for the packet propagation
461 sec=$(echo $now | awk -F. '{print $1}') && \
466 action gate base-time ${base_time} \
467 sched-entry OPEN 60000 -1 -1 \
468 sched-entry CLOSE 40000 -1 -1 \
474 sec=$(echo $now | awk -F. '{print $1}') && \
480 queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \
481 base-time ${base_time} \
482 sched-entry S 01 50000 \
483 sched-entry S 00 50000 \
486 The engine used to schedule the ingress gate operations is the same that the
487 one used for the tc-taprio offload. Therefore, the restrictions regarding the
488 fact that no two gate actions (either tc-gate or tc-taprio gates) may fire at
491 To come in handy, it is possible to share time-triggered virtual links across
500 base-time 0 \
501 sched-entry OPEN 50000000 -1 -1 \
502 sched-entry CLOSE 50000000 -1 -1 \
506 of dropped frames, which is a sum of frames dropped due to timing violations,
507 lack of destination ports and MTU enforcement checks). Byte-level counters are
514 and aims to showcase some potential switch caveats.
516 RMII PHY role and out-of-band signaling
517 ---------------------------------------
523 the 50 MHz clock themselves, in an attempt to be helpful.
524 On the other hand, the SJA1105 is only binary configurable - when in the RMII
525 MAC role it will also attempt to drive the clock signal. To prevent this from
528 In the RMII spec, the PHY can transmit extra out-of-band signals via RXD[1:0].
529 These are practically some extra code words (/J/ and /K/) sent prior to the
530 preamble of each frame. The MAC does not have this out-of-band signaling
532 So when the SJA1105 port is put in PHY role to avoid having 2 drivers on the
533 clock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105
534 emulates a PHY interface fully and generates the /J/ and /K/ symbols prior to
535 frame preambles, which the real PHY is not expected to understand. So the PHY
536 simply encodes the extra symbols received from the SJA1105-as-PHY onto the
537 100Base-Tx wire.
542 The take-away is that in RMII mode, the SJA1105 must be let to drive the
543 reference clock if connected to a PHY.
545 RGMII fixed-link and internal delays
546 ------------------------------------
549 tunable delay lines as part of the MAC, which can be used to establish the
551 When powered up, these can shift the Rx and Tx clocks with a phase difference
553 The catch is that the delay lines need to lock onto a clock signal with a
560 In the situation where the switch port is connected through an RGMII fixed-link
561 to a link partner whose link state life cycle is outside the control of Linux
564 The take-away is that in RGMII mode, the switch's internal delays are only
567 the fixed-link are under control of the same Linux system).
568 As to why would a fixed-link interface ever change link speeds: there are
570 their driver inevitably needs to change the speed and clock frequency if it's
571 required to work at gigabit.
574 ---------------------------
576 The SJA1105 does not have an MDIO bus and does not perform in-band AN either.
578 A board would need to hook up the PHYs connected to the switch to any other
579 MDIO bus available to Linux within the system (e.g. to the DSA master's MDIO