Lines Matching full:coresight
2 Coresight CPU Debug Module
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
107 power down in the way that the CoreSight / Debug designers anticipated.
120 See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details.
183 coresight-cpu-debug 850000.debug: CPU[0]:
184 coresight-cpu-debug 850000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)
185 coresight-cpu-debug 850000.debug: EDPCSR: handle_IPI+0x174/0x1d8
186 coresight-cpu-debug 850000.debug: EDCIDSR: 00000000
187 …coresight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI…
188 coresight-cpu-debug 852000.debug: CPU[1]:
189 coresight-cpu-debug 852000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)
190 coresight-cpu-debug 852000.debug: EDPCSR: debug_notifier_call+0x23c/0x358
191 coresight-cpu-debug 852000.debug: EDCIDSR: 00000000
192 …coresight-cpu-debug 852000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI…