Lines Matching refs:r0
135 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
189 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
205 ldr r0, [r2]
236 mov r4, r0
238 mov r0, #TEGRA_FLUSH_CACHE_ALL
240 mov r0, r4
256 add r3, r3, r0
258 mov32 r0, tegra30_tear_down_core
260 sub r0, r0, r1
262 add r0, r0, r1
276 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
280 mov r0, #0 @ power mode flags (!hotplug)
282 mov r0, #1 @ never return here
321 mov32 r0, TEGRA_CLK_RESET_BASE
324 str r1, [r0, #CLK_RESET_SCLK_BURST]
325 str r1, [r0, #CLK_RESET_CCLK_BURST]
327 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
328 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
334 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
335 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
336 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
349 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
350 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
351 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
362 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
363 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
366 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
367 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
369 pll_locked r1, r0, CLK_RESET_PLLM_BASE
370 pll_locked r1, r0, CLK_RESET_PLLP_BASE
371 pll_locked r1, r0, CLK_RESET_PLLA_BASE
372 pll_locked r1, r0, CLK_RESET_PLLC_BASE
383 pll_locked r1, r0, CLK_RESET_PLLX_BASE
385 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
387 str r1, [r0, #CLK_RESET_PLLP_BASE]
390 str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
401 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
404 str r4, [r0, #CLK_RESET_SCLK_BURST]
408 str r4, [r0, #CLK_RESET_CCLK_BURST]
418 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
419 movteq r0, #:upper16:TEGRA_EMC_BASE
421 movweq r0, #:lower16:TEGRA_EMC0_BASE
422 movteq r0, #:upper16:TEGRA_EMC0_BASE
424 movweq r0, #:lower16:TEGRA124_EMC_BASE
425 movteq r0, #:upper16:TEGRA124_EMC_BASE
429 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
431 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
433 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
436 ldr r1, [r0, #EMC_CFG_DIG_DLL]
438 str r1, [r0, #EMC_CFG_DIG_DLL]
440 emc_timing_update r1, r0
445 cmpeq r0, r1
447 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
450 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
453 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
457 ldr r1, [r0, #EMC_CFG]
459 str r1, [r0, #EMC_CFG]
462 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
465 streq r1, [r0, #EMC_NOP]
466 streq r1, [r0, #EMC_NOP]
468 emc_device_mask r1, r0
471 ldr r2, [r0, #EMC_EMC_STATUS]
478 ldr r2, [r0, #EMC_FBIO_CFG5]
486 str r2, [r0, #EMC_ZQ_CAL]
496 str r2, [r0, #EMC_ZQ_CAL]
505 str r2, [r0, #EMC_MRW]
515 str r2, [r0, #EMC_MRW]
522 str r1, [r0, #EMC_REQ_CTRL]
524 str r1, [r0, #EMC_ZCAL_INTERVAL]
526 str r1, [r0, #EMC_CFG]
528 emc_timing_update r1, r0
534 cmp r0, r1
535 movne r0, r1
540 mov32 r0, TEGRA_PMC_BASE
541 ldr r0, [r0, #PMC_SCRATCH41]
542 ret r0 @ jump to tegra_resume
623 mov r0, #(1 << 28)
624 str r0, [r5, #CLK_RESET_SCLK_BURST]
629 str r0, [r5, #CLK_RESET_CCLK_BURST]
630 mov r0, #0
631 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
632 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
635 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
636 orr r0, r0, #MSELECT_CLKM
637 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
645 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
646 bic r0, r0, #(1 << 12)
647 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
652 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
653 orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
654 bic r0, r0, #(1 << 30)
655 str r0, [r5, #CLK_RESET_PLLP_BASE]
657 mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
658 str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
660 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
661 bic r0, r0, #(1 << 30)
662 str r0, [r5, #CLK_RESET_PLLA_BASE]
663 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
664 bic r0, r0, #(1 << 30)
665 str r0, [r5, #CLK_RESET_PLLC_BASE]
666 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
667 bic r0, r0, #(1 << 30)
668 str r0, [r5, #CLK_RESET_PLLX_BASE]
680 mov r0, #(1 << 24)
681 str r0, [r5, #CLK_RESET_SCLK_BURST]
697 ldr r0, [r6, r2]
698 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
699 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
700 str r0, [r6, r2]
704 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
705 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
706 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
709 str r0, [r6, r2]
711 ldr r0, [r6, r2] /* memory barrier */
751 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
753 ldr r1, [r0]
764 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
766 ldreq r0, =TEGRA_EMC0_BASE
768 ldreq r0, =TEGRA124_EMC_BASE
773 str r1, [r0, #EMC_ZCAL_INTERVAL]
774 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
775 ldr r1, [r0, #EMC_CFG]
778 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
780 emc_timing_update r1, r0
787 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
792 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
795 ldr r1, [r0, #EMC_EMC_STATUS]
800 str r1, [r0, #EMC_SELF_REF]
802 emc_device_mask r1, r0
805 ldr r2, [r0, #EMC_EMC_STATUS]
811 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
814 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
815 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
819 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
821 emc_timing_update r1, r0
827 cmp r0, r1
828 movne r0, r1