Lines Matching refs:invalidate
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
194 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
213 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
218 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
241 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
277 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
337 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
345 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
351 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
354 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
388 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
389 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4