Lines Matching refs:r0
41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 bic r0, r0, #0x1800 @ ...iz...........
43 bic r0, r0, #0x0006 @ .............ca.
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
69 ret r0
80 mov r0, #0
81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
91 mov r0, #0
92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
134 sub r3, r1, r0 @ calculate total size
138 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
139 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 add r0, r0, #CACHE_DLINESIZE
141 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
143 add r0, r0, #CACHE_DLINESIZE
144 cmp r0, r1
176 bic r0, r0, #CACHE_DLINESIZE - 1
177 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
178 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
179 add r0, r0, #CACHE_DLINESIZE
180 cmp r0, r1
182 mcr p15, 0, r0, c7, c10, 4 @ drain WB
183 mov r0, #0
196 add r1, r0, r1
197 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
198 add r0, r0, #CACHE_DLINESIZE
199 cmp r0, r1
201 mov r0, #0
202 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
203 mcr p15, 0, r0, c7, c10, 4 @ drain WB
220 tst r0, #CACHE_DLINESIZE - 1
221 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
224 bic r0, r0, #CACHE_DLINESIZE - 1
225 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
226 add r0, r0, #CACHE_DLINESIZE
227 cmp r0, r1
229 mcr p15, 0, r0, c7, c10, 4 @ drain WB
243 bic r0, r0, #CACHE_DLINESIZE - 1
244 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
245 add r0, r0, #CACHE_DLINESIZE
246 cmp r0, r1
248 mcr p15, 0, r0, c7, c10, 4 @ drain WB
260 bic r0, r0, #CACHE_DLINESIZE - 1
262 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
263 add r0, r0, #CACHE_DLINESIZE
264 cmp r0, r1
266 mcr p15, 0, r0, c7, c10, 4 @ drain WB
276 add r1, r1, r0
300 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
301 add r0, r0, #CACHE_DLINESIZE
304 mcr p15, 0, r0, c7, c10, 4 @ drain WB
320 orr r0, r0, #0x18 @ cache the page table in L2
321 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
334 mov r0, r0
335 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
336 mcr p15, 0, r0, c7, c10, 4 @ drain WB
352 stmia r0, {r4 - r9} @ store cp regs
357 ldmia r0, {r4 - r9} @ load cp regs
370 mov r0, r9 @ control register
377 mov r0, #0
378 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
379 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
380 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
384 mov r0, #0 @ don't allow CP access