Lines Matching refs:x1
52 cmp x4, x1
61 invalidate_icache_by_line x0, x1, x2, x3, 9f
64 uaccess_ttbr0_disable x1, x2
89 invalidate_icache_by_line x0, x1, x2, x3, 2f
92 uaccess_ttbr0_disable x1, x2
109 dcache_by_line_op civac, sy, x0, x1, x2, x3
127 dcache_by_line_op cvau, ish, x0, x1, x2, x3
150 add x1, x1, x0
153 tst x1, x3 // end cache line aligned?
154 bic x1, x1, x3
156 dc civac, x1 // clean & invalidate D / U line
164 cmp x0, x1
189 dcache_by_line_op cvac, sy, x0, x1, x2, x3
207 dcache_by_line_op cvap, sy, x0, x1, x2, x3
220 dcache_by_line_op civac, sy, x0, x1, x2, x3