116 typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...);
171 	u64 pal_proc;
172 	u64 sal_proc;
173 	u64 gp;
186 	u64 addr;		/* physical address of memory */
203 	u64 addr;		/* virtual address of area covered */
204 	u64 page_size;		/* encoded page size */
212 	u64 domain_info;	/* physical address of domain info table */
216 	u64 proc_count;		/* number of processors in domain */
217 	u64 proc_list;		/* physical address of LID array */
221 	u64 id  : 8;		/* id of processor */
222 	u64 eid : 8;		/* eid of processor */
232 	u64 vector;		/* interrupt vector in range 0x10-0xff */
328 	u64 id;				/* Unique monotonically increasing ID */
364 		u64 check_info              : 1,
371 	u64 check_info;
372 	u64 requestor_identifier;
373 	u64 responder_identifier;
374 	u64 target_identifier;
375 	u64 precise_ip;
380 		u64 minstate        : 1,
389 	u64 br[8];
390 	u64 cr[128];
391 	u64 ar[128];
392 	u64 rr[8];
397 	u64 regs[5];
398 	u64 reserved;
404 		u64 proc_error_map      : 1,
416 	u64 proc_error_map;
417 	u64 proc_state_parameter;
418 	u64 proc_cr_lid;
452 		u64 error_status    : 1,
471 	u64 error_status;
472 	u64 physical_addr;
473 	u64 addr_mask;
482 	u64 requestor_id;
483 	u64 responder_id;
484 	u64 target_id;
485 	u64 bus_spec_data;
493 		u64 record_id       : 1,
521 		u64 err_status      : 1,
533 	u64 err_status;
537 	u64 bus_address;
538 	u64 bus_data;
539 	u64 bus_cmd;
540 	u64 requestor_id;
541 	u64 responder_id;
542 	u64 target_id;
549 		u64 event_type      : 1,
564 		u64 err_status      : 1,
572 	u64 err_status;
585 	u64 reg_data_pairs[1];
597 		u64 err_status      : 1,
602 	u64 err_status;
610 		u64 err_status      : 1,
618 	u64 err_status;
619 	u64 requestor_id;
620 	u64 responder_id;
621 	u64 target_id;
622 	u64 bus_spec_data;
629 		u64 err_status      : 1,
637 	u64 err_status;
638 	u64 requestor_id;
639 	u64 responder_id;
640 	u64 target_id;
641 	u64 bus_spec_data;
670 extern s64 ia64_sal_cache_flush (u64 cache_type);
687 ia64_sal_clear_state_info (u64 sal_info_type)  in ia64_sal_clear_state_info()
699 static inline u64
700 ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info)  in ia64_sal_get_state_info()
715 static inline u64
716 ia64_sal_get_state_info_size (u64 sal_info_type)  in ia64_sal_get_state_info_size()
747 ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always)  in ia64_sal_mc_set_params()
757 ia64_sal_pci_config_read (u64 pci_config_addr, int type, u64 size, u64 *value)  in ia64_sal_pci_config_read()
768 ia64_sal_pci_config_write (u64 pci_config_addr, int type, u64 size, u64 value)  in ia64_sal_pci_config_write()
781 ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)  in ia64_sal_register_physical_addr()
795 ia64_sal_set_vectors (u64 vector_type,  in ia64_sal_set_vectors()
796 		      u64 handler_addr1, u64 gp1, u64 handler_len1,  in ia64_sal_set_vectors()
797 		      u64 handler_addr2, u64 gp2, u64 handler_len2)  in ia64_sal_set_vectors()
809 ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,  in ia64_sal_update_pal()
810 		     u64 *error_code, u64 *scratch_buf_size_needed)  in ia64_sal_update_pal()
839 extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
848 extern int ia64_sal_oemcall(struct ia64_sal_retval *, u64, u64, u64, u64, u64,
849 			    u64, u64, u64);
850 extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64,
851 				   u64, u64, u64, u64, u64);
852 extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64,
853 				      u64, u64, u64, u64, u64);
865 	u64 rr[8];		/* Region Registers */
866 	u64 br[6];		/* br0:
868 	u64 gr1;		/* SAL:GP */
869 	u64 gr12;		/* SAL:SP */
870 	u64 gr13;		/* SAL: Task Pointer */
871 	u64 fpsr;
872 	u64 pfs;
873 	u64 rnat;
874 	u64 unat;
875 	u64 bspstore;
876 	u64 dcr;		/* Default Control Register */
877 	u64 iva;
878 	u64 pta;
879 	u64 itv;
880 	u64 pmv;
881 	u64 cmcv;
882 	u64 lrr[2];
883 	u64 gr[4];
884 	u64 pr;			/* Predicate registers */
885 	u64 lc;			/* Loop Count */