Lines Matching refs:x1
36 #cpus = <0x1>;
54 xlnx,allow-dcache-wr = <0x1>;
55 xlnx,allow-icache-wr = <0x1>;
58 xlnx,d-lmb = <0x1>;
60 xlnx,d-plb = <0x1>;
63 xlnx,dcache-always-used = <0x1>;
66 xlnx,dcache-use-fsl = <0x1>;
67 xlnx,debug-enabled = <0x1>;
68 xlnx,div-zero-exception = <0x1>;
70 xlnx,dynamic-bus-sizing = <0x1>;
71 xlnx,edge-is-positive = <0x1>;
73 xlnx,endianness = <0x1>;
74 xlnx,fpu-exception = <0x1>;
78 xlnx,i-lmb = <0x1>;
80 xlnx,i-plb = <0x1>;
81 xlnx,icache-always-used = <0x1>;
83 xlnx,icache-use-fsl = <0x1>;
84 xlnx,ill-opcode-exception = <0x1>;
86 xlnx,interconnect = <0x1>;
93 xlnx,number-of-pc-brk = <0x1>;
96 xlnx,opcode-0x0-illegal = <0x1>;
102 xlnx,unaligned-exceptions = <0x1>;
103 xlnx,use-barrel = <0x1>;
104 xlnx,use-dcache = <0x1>;
105 xlnx,use-div = <0x1>;
106 xlnx,use-ext-brk = <0x1>;
107 xlnx,use-ext-nm-brk = <0x1>;
111 xlnx,use-icache = <0x1>;
112 xlnx,use-interrupt = <0x1>;
114 xlnx,use-msr-instr = <0x1>;
115 xlnx,use-pcmp-instr = <0x1>;
128 xlnx,include-datawidth-matching-0 = <0x1>;
133 xlnx,include-plb-ipif = <0x1>;
134 xlnx,include-wrbuf = <0x1>;
155 xlnx,num-banks-mem = <0x1>;
195 xlnx,xcl0-writexfer = <0x1>;
197 xlnx,xcl1-writexfer = <0x1>;
199 xlnx,xcl2-writexfer = <0x1>;
201 xlnx,xcl3-writexfer = <0x1>;
215 xlnx,bus2core-clk-ratio = <0x1>;
216 xlnx,phy-type = <0x1>;
217 xlnx,phyaddr = <0x1>;
232 xlnx,gpo-width = <0x1>;
249 xlnx,interrupt-present = <0x1>;
250 xlnx,is-bidir = <0x1>;
251 xlnx,is-bidir-2 = <0x1>;
325 xlnx,interconnect = <0x1>;
327 xlnx,mb-dbg-ports = <0x1>;
329 xlnx,use-uart = <0x1>;
359 xlnx,gen0-assert = <0x1>;
360 xlnx,gen1-assert = <0x1>;
362 xlnx,trig0-assert = <0x1>;
363 xlnx,trig1-assert = <0x1>;