Lines Matching refs:u32

41 	u32	ddma_config;
42 	u32	ddma_intstat;
43 	u32	ddma_throttle;
44 	u32	ddma_inten;
56 	u32	ddma_cfg;	/* See below */
57 	u32	ddma_desptr;	/* 32-byte aligned pointer to descriptor */
58 	u32	ddma_statptr;	/* word aligned pointer to status word */
59 	u32	ddma_dbell;	/* A write activates channel operation */
60 	u32	ddma_irq;	/* If bit 0 set, interrupt pending */
61 	u32	ddma_stat;	/* See below */
62 	u32	ddma_bytecnt;	/* Byte count, valid only when chan idle */
93 	u32	dscr_cmd0;		/* See below */
94 	u32	dscr_cmd1;		/* See below */
95 	u32	dscr_source0;		/* source phys address */
96 	u32	dscr_source1;		/* See below */
97 	u32	dscr_dest0;		/* Destination address */
98 	u32	dscr_dest1;		/* See below */
99 	u32	dscr_stat;		/* completion status */
100 	u32	dscr_nxtptr;		/* Next descriptor pointer (mostly) */
105 	u32	sw_status;
106 	u32	sw_context;
107 	u32	sw_reserved[6];
308 	u32	dev_id;
309 	u32	dev_flags;
310 	u32	dev_tsize;
311 	u32	dev_devwidth;
312 	u32	dev_physaddr;		/* If FIFO */
313 	u32	dev_intlevel;
314 	u32	dev_intpolarity;
321 	u32			chan_flags;
322 	u32			chan_index;
327 	u32			cdb_membase; /* kmalloc base of above */
348 extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
355 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
358 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
361 u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
362 u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
365 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
367 void au1xxx_dbdma_stop(u32 chanid);
368 void au1xxx_dbdma_start(u32 chanid);
369 void au1xxx_dbdma_reset(u32 chanid);
370 u32 au1xxx_get_dma_residue(u32 chanid);
372 void au1xxx_dbdma_chan_free(u32 chanid);
373 void au1xxx_dbdma_dump(u32 chanid);
375 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
377 u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
378 extern void au1xxx_ddma_del_device(u32 devid);