Lines Matching refs:t1
179 1: PTR_L t1, VPEBOOTCFG_PC(v1)
182 jr t1
242 PTR_LA t1, 1f
243 jr.hb t1
273 sll t1, ta1, VPECONF0_XTC_SHIFT
274 or t0, t0, t1
311 li t1, COREBOOTCFG_SIZE
312 mul t0, t0, t1
313 PTR_LA t1, mips_cps_core_bootcfg
314 PTR_L t1, 0(t1)
315 PTR_ADDU v0, t0, t1
333 mfc0 t1, CP0_MVPCONF0
334 srl t1, t1, MVPCONF0_PVPE_SHIFT
335 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
336 addiu t1, t1, 1
339 clz t1, t1
341 subu t1, t2, t1
343 sll t1, t2, t1
344 addiu t1, t1, -1
348 and t9, t9, t1
352 li t1, VPEBOOTCFG_SIZE
353 mul v1, t9, t1
371 PTR_L t1, GCR_CPC_BASE_OFS(t3)
373 and t1, t1, t2
375 PTR_ADD t1, t1, t2
378 PTR_S ta2, CPC_CL_VC_RUN_OFS(t1)
382 PTR_S ta2, CPC_CL_VC_STOP_OFS(t1)
397 PTR_LA t1, 1f
398 jr.hb t1
400 1: mfc0 t1, CP0_MVPCONTROL
401 ori t1, t1, MVPCONTROL_VPC
402 mtc0 t1, CP0_MVPCONTROL
437 lw t1, VPEBOOTCFG_PC(t0)
438 mttc0 t1, CP0_TCRESTART
441 lw t1, VPEBOOTCFG_SP(t0)
442 mttgpr t1, sp
445 lw t1, VPEBOOTCFG_GP(t0)
446 mttgpr t1, gp
473 li t1, ~TCSTATUS_IXMT
474 and t0, t0, t1
493 mfc0 t1, CP0_MVPCONTROL
494 xori t1, t1, MVPCONTROL_VPC
495 mtc0 t1, CP0_MVPCONTROL
543 li t1, 2
544 sllv t0, t1, t0
547 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
548 xori t2, t1, 0x7
551 addiu t1, t1, 1
552 sllv t1, t3, t1
556 mul t1, t1, t0
557 mul t1, t1, t2
560 PTR_ADD a1, a0, t1
570 li t1, 2
571 sllv t0, t1, t0
574 _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
575 xori t2, t1, 0x7
578 addiu t1, t1, 1
579 sllv t1, t3, t1
583 mul t1, t1, t0
584 mul t1, t1, t2
587 PTR_ADDU a1, a0, t1
617 psstate t1
625 psstate t1