Lines Matching refs:opcode
519 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) in simulate_ll() argument
530 offset = opcode & OFFSET; in simulate_ll()
535 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); in simulate_ll()
553 regs->regs[(opcode & RT) >> 16] = value; in simulate_ll()
558 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) in simulate_sc() argument
570 offset = opcode & OFFSET; in simulate_sc()
575 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); in simulate_sc()
576 reg = (opcode & RT) >> 16; in simulate_sc()
606 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) in simulate_llsc() argument
608 if ((opcode & OPCODE) == LL) { in simulate_llsc()
611 return simulate_ll(regs, opcode); in simulate_llsc()
613 if ((opcode & OPCODE) == SC) { in simulate_llsc()
616 return simulate_sc(regs, opcode); in simulate_llsc()
661 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) in simulate_rdhwr_normal() argument
663 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { in simulate_rdhwr_normal()
664 int rd = (opcode & RD) >> 11; in simulate_rdhwr_normal()
665 int rt = (opcode & RT) >> 16; in simulate_rdhwr_normal()
675 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode) in simulate_rdhwr_mm() argument
677 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { in simulate_rdhwr_mm()
678 int rd = (opcode & MM_RS) >> 16; in simulate_rdhwr_mm()
679 int rt = (opcode & MM_RT) >> 21; in simulate_rdhwr_mm()
688 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) in simulate_sync() argument
690 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { in simulate_sync()
713 unsigned int opcode) in simulate_loongson3_cpucfg() argument
715 int op = opcode & OPCODE; in simulate_loongson3_cpucfg()
716 int op2 = opcode & CSR_OPCODE2_MASK; in simulate_loongson3_cpucfg()
717 int csr_func = (opcode & CSR_FUNC_MASK) >> 16; in simulate_loongson3_cpucfg()
720 int rd = (opcode & RD) >> 11; in simulate_loongson3_cpucfg()
721 int rs = (opcode & RS) >> 21; in simulate_loongson3_cpucfg()
815 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, in simulate_fp() argument
818 union mips_instruction inst = { .word = opcode }; in simulate_fp()
824 switch (inst.i_format.opcode) { in simulate_fp()
952 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, in simulate_fp() argument
1023 unsigned int opcode, bcode; in do_bp() local
1049 opcode = (instr[0] << 16) | instr[1]; in do_bp()
1050 bcode = (opcode >> 6) & ((1 << 20) - 1); in do_bp()
1053 if (__get_user(opcode, (unsigned int __user *)epc)) in do_bp()
1055 bcode = (opcode >> 6) & ((1 << 20) - 1); in do_bp()
1114 u32 opcode, tcode = 0; in do_tr() local
1130 opcode = (instr[0] << 16) | instr[1]; in do_tr()
1132 if (!(opcode & OPCODE)) in do_tr()
1133 tcode = (opcode >> 12) & ((1 << 4) - 1); in do_tr()
1135 if (__get_user(opcode, (u32 __user *)epc)) in do_tr()
1138 if (!(opcode & OPCODE)) in do_tr()
1139 tcode = (opcode >> 6) & ((1 << 10) - 1); in do_tr()
1160 unsigned int opcode = 0; in do_ri() local
1169 likely(get_user(opcode, epc) >= 0)) { in do_ri()
1172 status = mipsr2_decoder(regs, opcode, &fcr31); in do_ri()
1202 if (unlikely(get_user(opcode, epc) < 0)) in do_ri()
1206 status = simulate_llsc(regs, opcode); in do_ri()
1209 status = simulate_rdhwr_normal(regs, opcode); in do_ri()
1212 status = simulate_sync(regs, opcode); in do_ri()
1215 status = simulate_fp(regs, opcode, old_epc, old31); in do_ri()
1219 status = simulate_loongson3_cpucfg(regs, opcode); in do_ri()
1228 opcode = mmop[0]; in do_ri()
1229 opcode = (opcode << 16) | mmop[1]; in do_ri()
1232 status = simulate_rdhwr_mm(regs, opcode); in do_ri()
1410 unsigned int opcode; in do_cpu() local
1425 opcode = 0; in do_cpu()
1432 if (unlikely(get_user(opcode, epc) < 0)) in do_cpu()
1436 status = simulate_llsc(regs, opcode); in do_cpu()