Lines Matching refs:t1
60 mfcr t1, t0
63 or t1, t1, t2
64 mtcr t1, t0
67 mfcr t1, t0
68 ori t1, 0x1000 /* Enable Icache partitioning */
69 mtcr t1, t0
72 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
73 mtcr t1, t0
83 li t1, (1 << 29) /* ELPA bit */
84 or t0, t1
96 slt t1, t0, 0x1200
97 beqz t1, 15f
102 li t1, LSU_DEBUG_ADDR
109 mtcr v1, t1
111 mfcr v1, t1
117 mtcr v1, t1
119 mfcr v1, t1
132 li t1, 0x80010000
135 bne t0, t1, 16b
175 li t1, 0x1500 /* XLP 9xx */
176 beq t0, t1, 2f /* does not need to set coherent */
179 li t1, 0x1300 /* XLP 5xx */
180 beq t0, t1, 2f /* does not need to set coherent */
185 mfc0 t1, CP0_EBASE
186 srl t1, 5
187 andi t1, 0x3 /* t1 <- node */
189 mul t3, t2, t1 /* t3 = node * 0x40000 */
192 li t1, 0x1
193 sll t0, t1, t0
197 lw t1, 0(t2)
198 and t1, t1, t0
199 sw t1, 0(t2)
202 lw t1, 0(t2)
221 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
224 or t2, t2, t1
247 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
248 subu t1, 0x3 /* 4-thread per core mode? */
249 bnez t1, 2f
253 li t1, 0x55
254 mtcr t1, t0
261 move t1, zero
263 ori t1, ST0_KX
265 mtc0 t1, CP0_STATUS
271 ADDIU t1, t3, BOOT_CPU_READY
273 PTR_ADDU t1, v1
275 sw t2, 0(t1)