267 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);  in pnv_eeh_find_ecap()  local
271 	if (!edev || !edev->pcie_cap)  in pnv_eeh_find_ecap()
326 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);  in pnv_eeh_probe()  local
338 	if (!edev || edev->pe)  in pnv_eeh_probe()
342 	if (edev->pdev) {  in pnv_eeh_probe()
346 		return edev;  in pnv_eeh_probe()
353 	eeh_edev_dbg(edev, "Probing device\n");  in pnv_eeh_probe()
356 	edev->mode	&= 0xFFFFFF00;  in pnv_eeh_probe()
357 	edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);  in pnv_eeh_probe()
358 	edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);  in pnv_eeh_probe()
359 	edev->af_cap   = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF);  in pnv_eeh_probe()
360 	edev->aer_cap  = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);  in pnv_eeh_probe()
362 		edev->mode |= EEH_DEV_BRIDGE;  in pnv_eeh_probe()
363 		if (edev->pcie_cap) {  in pnv_eeh_probe()
364 			pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,  in pnv_eeh_probe()
368 				edev->mode |= EEH_DEV_ROOT_PORT;  in pnv_eeh_probe()
370 				edev->mode |= EEH_DEV_DS_PORT;  in pnv_eeh_probe()
374 	edev->pe_config_addr = phb->ioda.pe_rmap[config_addr];  in pnv_eeh_probe()
379 	ret = eeh_pe_tree_insert(edev, upstream_pe);  in pnv_eeh_probe()
381 		eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n", ret);  in pnv_eeh_probe()
411 		edev->pe->state |= EEH_PE_CFG_RESTRICTED;  in pnv_eeh_probe()
419 	if (!(edev->pe->state & EEH_PE_PRI_BUS)) {  in pnv_eeh_probe()
420 		edev->pe->bus = pci_find_bus(hose->global_number,  in pnv_eeh_probe()
422 		if (edev->pe->bus)  in pnv_eeh_probe()
423 			edev->pe->state |= EEH_PE_PRI_BUS;  in pnv_eeh_probe()
437 	eeh_save_bars(edev);  in pnv_eeh_probe()
439 	eeh_edev_dbg(edev, "EEH enabled on device\n");  in pnv_eeh_probe()
441 	return edev;  in pnv_eeh_probe()
804 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);  in __pnv_eeh_bridge_reset()  local
805 	int aer = edev ? edev->aer_cap : 0;  in __pnv_eeh_bridge_reset()
817 			eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,  in __pnv_eeh_bridge_reset()
820 			eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,  in __pnv_eeh_bridge_reset()
824 		eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);  in __pnv_eeh_bridge_reset()
826 		eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);  in __pnv_eeh_bridge_reset()
831 		eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);  in __pnv_eeh_bridge_reset()
833 		eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);  in __pnv_eeh_bridge_reset()
839 			eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,  in __pnv_eeh_bridge_reset()
842 			eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,  in __pnv_eeh_bridge_reset()
911 	struct eeh_dev *edev = pdn->edev;  in pnv_eeh_wait_for_pending()  local
916 		eeh_ops->read_config(edev, pos, 2, &status);  in pnv_eeh_wait_for_pending()
931 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);  in pnv_eeh_do_flr()  local
934 	if (WARN_ON(!edev->pcie_cap))  in pnv_eeh_do_flr()
937 	eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, &reg);  in pnv_eeh_do_flr()
945 					 edev->pcie_cap + PCI_EXP_DEVSTA,  in pnv_eeh_do_flr()
947 		eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,  in pnv_eeh_do_flr()
950 		eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,  in pnv_eeh_do_flr()
955 		eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,  in pnv_eeh_do_flr()
958 		eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,  in pnv_eeh_do_flr()
969 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);  in pnv_eeh_do_af_flr()  local
972 	if (WARN_ON(!edev->af_cap))  in pnv_eeh_do_af_flr()
975 	eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap);  in pnv_eeh_do_af_flr()
988 					 edev->af_cap + PCI_AF_CTRL,  in pnv_eeh_do_af_flr()
990 		eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL,  in pnv_eeh_do_af_flr()
995 		eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0);  in pnv_eeh_do_af_flr()
1005 	struct eeh_dev *edev;  in pnv_eeh_reset_vf_pe()  local
1010 	edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);  in pnv_eeh_reset_vf_pe()
1011 	pdn = eeh_dev_to_pdn(edev);  in pnv_eeh_reset_vf_pe()
1210 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);  in pnv_eeh_cfg_blocked()  local
1212 	if (!edev || !edev->pe)  in pnv_eeh_cfg_blocked()
1220 	if (edev->physfn && (edev->pe->state & EEH_PE_RESET))  in pnv_eeh_cfg_blocked()
1223 	if (edev->pe->state & EEH_PE_CFG_BLOCKED)  in pnv_eeh_cfg_blocked()
1229 static int pnv_eeh_read_config(struct eeh_dev *edev,  in pnv_eeh_read_config()  argument
1232 	struct pci_dn *pdn = eeh_dev_to_pdn(edev);  in pnv_eeh_read_config()
1245 static int pnv_eeh_write_config(struct eeh_dev *edev,  in pnv_eeh_write_config()  argument
1248 	struct pci_dn *pdn = eeh_dev_to_pdn(edev);  in pnv_eeh_write_config()
1603 static int pnv_eeh_restore_config(struct eeh_dev *edev)  in pnv_eeh_restore_config()  argument
1608 	if (!edev)  in pnv_eeh_restore_config()
1611 	if (edev->physfn)  in pnv_eeh_restore_config()
1614 	phb = edev->controller->private_data;  in pnv_eeh_restore_config()
1616 			      OPAL_REINIT_PCI_DEV, edev->bdfn);  in pnv_eeh_restore_config()
1620 			__func__, edev->bdfn, ret);  in pnv_eeh_restore_config()