510 static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)  in ipic_write()  function
531 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_unmask_irq()
547 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_mask_irq()
566 	ipic_write(ipic->regs, ipic_info[src].ack, temp);  in ipic_ack_irq()
586 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_mask_irq_and_ack()
589 	ipic_write(ipic->regs, ipic_info[src].ack, temp);  in ipic_mask_irq_and_ack()
649 		ipic_write(ipic->regs, IPIC_SECNR, vnew);  in ipic_set_irq_type()
723 	ipic_write(ipic->regs, IPIC_SICNR, 0x0);  in ipic_init()
740 	ipic_write(ipic->regs, IPIC_SICFR, temp);  in ipic_init()
746 	ipic_write(ipic->regs, IPIC_SERCR, temp);  in ipic_init()
756 	ipic_write(ipic->regs, IPIC_SEMSR, temp);  in ipic_init()
761 	ipic_write(ipic->regs, IPIC_SIMSR_H, 0);  in ipic_init()
762 	ipic_write(ipic->regs, IPIC_SIMSR_L, 0);  in ipic_init()
772 	ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
773 	ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
774 	ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
775 	ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
776 	ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
777 	ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);  in ipic_set_default_priority()
787 	ipic_write(primary_ipic->regs, IPIC_SERSR, mask);  in ipic_clear_mcp_status()
841 		ipic_write(ipic->regs, IPIC_SIMSR_H, 0);  in ipic_suspend()
842 		ipic_write(ipic->regs, IPIC_SIMSR_L, 0);  in ipic_suspend()
843 		ipic_write(ipic->regs, IPIC_SEMSR, 0);  in ipic_suspend()
844 		ipic_write(ipic->regs, IPIC_SERMR, 0);  in ipic_suspend()
854 	ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);  in ipic_resume()
855 	ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);  in ipic_resume()
856 	ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);  in ipic_resume()
857 	ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);  in ipic_resume()
858 	ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);  in ipic_resume()
859 	ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);  in ipic_resume()
860 	ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);  in ipic_resume()
861 	ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);  in ipic_resume()
862 	ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);  in ipic_resume()
863 	ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);  in ipic_resume()
864 	ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);  in ipic_resume()
865 	ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);  in ipic_resume()