199 	struct pci_pbm_info *pbm = dev_id;  in sabre_ue_intr()  local
200 	unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;  in sabre_ue_intr()
201 	unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;  in sabre_ue_intr()
220 	       pbm->name,  in sabre_ue_intr()
228 	       pbm->name,  in sabre_ue_intr()
232 	printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);  in sabre_ue_intr()
233 	printk("%s: UE Secondary errors [", pbm->name);  in sabre_ue_intr()
252 	psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);  in sabre_ue_intr()
259 	struct pci_pbm_info *pbm = dev_id;  in sabre_ce_intr()  local
260 	unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;  in sabre_ce_intr()
261 	unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;  in sabre_ce_intr()
279 	       pbm->name,  in sabre_ce_intr()
290 	       pbm->name,  in sabre_ce_intr()
295 	printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);  in sabre_ce_intr()
296 	printk("%s: CE Secondary errors [", pbm->name);  in sabre_ce_intr()
313 static void sabre_register_error_handlers(struct pci_pbm_info *pbm)  in sabre_register_error_handlers()  argument
315 	struct device_node *dp = pbm->op->dev.of_node;  in sabre_register_error_handlers()
317 	unsigned long base = pbm->controller_regs;  in sabre_register_error_handlers()
321 	if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)  in sabre_register_error_handlers()
346 	err = request_irq(op->archdata.irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);  in sabre_register_error_handlers()
349 		       pbm->name, err);  in sabre_register_error_handlers()
356 	err = request_irq(op->archdata.irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);  in sabre_register_error_handlers()
359 		       pbm->name, err);  in sabre_register_error_handlers()
361 			  "SABRE_PCIERR", pbm);  in sabre_register_error_handlers()
364 		       pbm->name, err);  in sabre_register_error_handlers()
407 static void sabre_scan_bus(struct pci_pbm_info *pbm, struct device *parent)  in sabre_scan_bus()  argument
419 		pbm->is_66mhz_capable = 1;  in sabre_scan_bus()
421 		pbm->is_66mhz_capable = 0;  in sabre_scan_bus()
435 	pbm->pci_bus = pci_scan_one_pbm(pbm, parent);  in sabre_scan_bus()
436 	if (!pbm->pci_bus)  in sabre_scan_bus()
439 	sabre_root_bus = pbm->pci_bus;  in sabre_scan_bus()
441 	apb_init(pbm->pci_bus);  in sabre_scan_bus()
443 	sabre_register_error_handlers(pbm);  in sabre_scan_bus()
446 static void sabre_pbm_init(struct pci_pbm_info *pbm,  in sabre_pbm_init()  argument
449 	psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE);  in sabre_pbm_init()
450 	pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR;  in sabre_pbm_init()
451 	pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR;  in sabre_pbm_init()
452 	pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL;  in sabre_pbm_init()
453 	sabre_scan_bus(pbm, &op->dev);  in sabre_pbm_init()
462 	struct pci_pbm_info *pbm;  in sabre_probe()  local
484 	pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);  in sabre_probe()
485 	if (!pbm) {  in sabre_probe()
496 	pbm->iommu = iommu;  in sabre_probe()
500 	pbm->portid = upa_portid;  in sabre_probe()
516 	pbm->controller_regs = pr_regs[0].phys_addr;  in sabre_probe()
522 		upa_writeq(0x0UL, pbm->controller_regs + clear_irq);  in sabre_probe()
526 		upa_writeq(0x0UL, pbm->controller_regs + clear_irq);  in sabre_probe()
531 		   pbm->controller_regs + SABRE_PCICTRL);  in sabre_probe()
534 	pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE;  in sabre_probe()
562 	err = psycho_iommu_init(pbm, tsbsize, vdma[0], dma_mask, SABRE_WRSYNC);  in sabre_probe()
569 	sabre_pbm_init(pbm, op);  in sabre_probe()
571 	pbm->next = pci_pbm_root;  in sabre_probe()
572 	pci_pbm_root = pbm;  in sabre_probe()
574 	dev_set_drvdata(&op->dev, pbm);  in sabre_probe()
579 	kfree(pbm->iommu);  in sabre_probe()
582 	kfree(pbm);  in sabre_probe()