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Lines Matching refs:x86_pmu

197 	if (pmi && x86_pmu.version >= 4)  in __intel_pmu_lbr_enable()
205 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask; in __intel_pmu_lbr_enable()
249 for (i = 0; i < x86_pmu.lbr_nr; i++) in intel_pmu_lbr_reset_32()
250 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_32()
257 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_lbr_reset_64()
258 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_64()
259 wrmsrl(x86_pmu.lbr_to + i, 0); in intel_pmu_lbr_reset_64()
260 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) in intel_pmu_lbr_reset_64()
261 wrmsrl(x86_pmu.lbr_info + i, 0); in intel_pmu_lbr_reset_64()
268 wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr); in intel_pmu_arch_lbr_reset()
275 if (!x86_pmu.lbr_nr) in intel_pmu_lbr_reset()
278 x86_pmu.lbr_reset(); in intel_pmu_lbr_reset()
291 rdmsrl(x86_pmu.lbr_tos, tos); in intel_pmu_lbr_tos()
320 int lbr_format = x86_pmu.intel_cap.lbr_format; in lbr_from_signext_quirk_needed()
365 wrmsrl(x86_pmu.lbr_from + idx, val); in wrlbr_from()
370 wrmsrl(x86_pmu.lbr_to + idx, val); in wrlbr_to()
375 wrmsrl(x86_pmu.lbr_info + idx, val); in wrlbr_info()
385 rdmsrl(x86_pmu.lbr_from + idx, val); in rdlbr_from()
397 rdmsrl(x86_pmu.lbr_to + idx, val); in rdlbr_to()
409 rdmsrl(x86_pmu.lbr_info + idx, val); in rdlbr_info()
442 bool need_info = x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO; in intel_pmu_lbr_restore()
449 mask = x86_pmu.lbr_nr - 1; in intel_pmu_lbr_restore()
455 for (; i < x86_pmu.lbr_nr; i++) { in intel_pmu_lbr_restore()
459 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO) in intel_pmu_lbr_restore()
463 wrmsrl(x86_pmu.lbr_tos, tos); in intel_pmu_lbr_restore()
476 if (!entries[x86_pmu.lbr_nr - 1].from) in intel_pmu_arch_lbr_restore()
479 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_arch_lbr_restore()
500 return x86_pmu.lbr_deep_c_reset && !rdlbr_from(0, NULL); in lbr_is_reset_in_cstate()
527 x86_pmu.lbr_restore(ctx); in __intel_pmu_lbr_restore()
534 bool need_info = x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO; in intel_pmu_lbr_save()
541 mask = x86_pmu.lbr_nr - 1; in intel_pmu_lbr_save()
543 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_lbr_save()
561 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_arch_lbr_save()
567 if (i < x86_pmu.lbr_nr) in intel_pmu_arch_lbr_save()
568 entries[x86_pmu.lbr_nr - 1].from = 0; in intel_pmu_arch_lbr_save()
591 x86_pmu.lbr_save(ctx); in __intel_pmu_lbr_save()
663 if (!x86_pmu.lbr_nr) in intel_pmu_lbr_add()
693 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0) in intel_pmu_lbr_add()
744 if (!x86_pmu.lbr_nr) in intel_pmu_lbr_del()
754 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0) in intel_pmu_lbr_del()
788 unsigned long mask = x86_pmu.lbr_nr - 1; in intel_pmu_lbr_read_32()
792 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_lbr_read_32()
802 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); in intel_pmu_lbr_read_32()
826 unsigned long mask = x86_pmu.lbr_nr - 1; in intel_pmu_lbr_read_64()
827 int lbr_format = x86_pmu.intel_cap.lbr_format; in intel_pmu_lbr_read_64()
831 int num = x86_pmu.lbr_nr; in intel_pmu_lbr_read_64()
896 if (abort && x86_pmu.lbr_double_abort && out > 0) in intel_pmu_lbr_read_64()
916 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) || !x86_pmu.lbr_br_type) in get_lbr_br_type()
924 if (static_cpu_has(X86_FEATURE_ARCH_LBR) && !x86_pmu.lbr_mispred) in get_lbr_mispred()
932 if (static_cpu_has(X86_FEATURE_ARCH_LBR) && !x86_pmu.lbr_mispred) in get_lbr_predicted()
941 !(x86_pmu.lbr_timed_lbr && info & LBR_INFO_CYC_CNT_VALID)) in get_lbr_cycles()
955 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_store_lbr()
1015 x86_pmu.lbr_read(cpuc); in intel_pmu_lbr_read()
1104 v = x86_pmu.lbr_sel_map[i]; in intel_pmu_setup_hw_lbr_filter()
1135 reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK); in intel_pmu_setup_hw_lbr_filter()
1139 (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)) in intel_pmu_setup_hw_lbr_filter()
1152 if (!x86_pmu.lbr_nr) in intel_pmu_setup_lbr_filter()
1165 if (x86_pmu.lbr_sel_map) in intel_pmu_setup_lbr_filter()
1567 x86_pmu.lbr_nr = 4; in intel_pmu_lbr_init_core()
1568 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_core()
1569 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; in intel_pmu_lbr_init_core()
1570 x86_pmu.lbr_to = MSR_LBR_CORE_TO; in intel_pmu_lbr_init_core()
1581 x86_pmu.lbr_nr = 16; in intel_pmu_lbr_init_nhm()
1582 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_nhm()
1583 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; in intel_pmu_lbr_init_nhm()
1584 x86_pmu.lbr_to = MSR_LBR_NHM_TO; in intel_pmu_lbr_init_nhm()
1586 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_nhm()
1587 x86_pmu.lbr_sel_map = nhm_lbr_sel_map; in intel_pmu_lbr_init_nhm()
1601 x86_pmu.lbr_nr = 16; in intel_pmu_lbr_init_snb()
1602 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_snb()
1603 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; in intel_pmu_lbr_init_snb()
1604 x86_pmu.lbr_to = MSR_LBR_NHM_TO; in intel_pmu_lbr_init_snb()
1606 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_snb()
1607 x86_pmu.lbr_sel_map = snb_lbr_sel_map; in intel_pmu_lbr_init_snb()
1628 x86_pmu.lbr_nr = 16; in intel_pmu_lbr_init_hsw()
1629 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_hsw()
1630 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; in intel_pmu_lbr_init_hsw()
1631 x86_pmu.lbr_to = MSR_LBR_NHM_TO; in intel_pmu_lbr_init_hsw()
1633 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_hsw()
1634 x86_pmu.lbr_sel_map = hsw_lbr_sel_map; in intel_pmu_lbr_init_hsw()
1647 x86_pmu.lbr_nr = 32; in intel_pmu_lbr_init_skl()
1648 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_skl()
1649 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; in intel_pmu_lbr_init_skl()
1650 x86_pmu.lbr_to = MSR_LBR_NHM_TO; in intel_pmu_lbr_init_skl()
1651 x86_pmu.lbr_info = MSR_LBR_INFO_0; in intel_pmu_lbr_init_skl()
1653 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_skl()
1654 x86_pmu.lbr_sel_map = hsw_lbr_sel_map; in intel_pmu_lbr_init_skl()
1680 x86_pmu.lbr_nr = 8; in intel_pmu_lbr_init_atom()
1681 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_atom()
1682 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; in intel_pmu_lbr_init_atom()
1683 x86_pmu.lbr_to = MSR_LBR_CORE_TO; in intel_pmu_lbr_init_atom()
1694 x86_pmu.lbr_nr = 8; in intel_pmu_lbr_init_slm()
1695 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_slm()
1696 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; in intel_pmu_lbr_init_slm()
1697 x86_pmu.lbr_to = MSR_LBR_CORE_TO; in intel_pmu_lbr_init_slm()
1699 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_slm()
1700 x86_pmu.lbr_sel_map = nhm_lbr_sel_map; in intel_pmu_lbr_init_slm()
1712 x86_pmu.lbr_nr = 8; in intel_pmu_lbr_init_knl()
1713 x86_pmu.lbr_tos = MSR_LBR_TOS; in intel_pmu_lbr_init_knl()
1714 x86_pmu.lbr_from = MSR_LBR_NHM_FROM; in intel_pmu_lbr_init_knl()
1715 x86_pmu.lbr_to = MSR_LBR_NHM_TO; in intel_pmu_lbr_init_knl()
1717 x86_pmu.lbr_sel_mask = LBR_SEL_MASK; in intel_pmu_lbr_init_knl()
1718 x86_pmu.lbr_sel_map = snb_lbr_sel_map; in intel_pmu_lbr_init_knl()
1721 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP) in intel_pmu_lbr_init_knl()
1722 x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS; in intel_pmu_lbr_init_knl()
1733 x86_pmu.lbr_nr * sizeof(struct lbr_entry); in get_lbr_state_size()
1776 x86_pmu.lbr_depth_mask = eax.split.lbr_depth_mask; in intel_pmu_arch_lbr_init()
1777 x86_pmu.lbr_deep_c_reset = eax.split.lbr_deep_c_reset; in intel_pmu_arch_lbr_init()
1778 x86_pmu.lbr_lip = eax.split.lbr_lip; in intel_pmu_arch_lbr_init()
1779 x86_pmu.lbr_cpl = ebx.split.lbr_cpl; in intel_pmu_arch_lbr_init()
1780 x86_pmu.lbr_filter = ebx.split.lbr_filter; in intel_pmu_arch_lbr_init()
1781 x86_pmu.lbr_call_stack = ebx.split.lbr_call_stack; in intel_pmu_arch_lbr_init()
1782 x86_pmu.lbr_mispred = ecx.split.lbr_mispred; in intel_pmu_arch_lbr_init()
1783 x86_pmu.lbr_timed_lbr = ecx.split.lbr_timed_lbr; in intel_pmu_arch_lbr_init()
1784 x86_pmu.lbr_br_type = ecx.split.lbr_br_type; in intel_pmu_arch_lbr_init()
1785 x86_pmu.lbr_nr = lbr_nr; in intel_pmu_arch_lbr_init()
1804 x86_pmu.lbr_from = MSR_ARCH_LBR_FROM_0; in intel_pmu_arch_lbr_init()
1805 x86_pmu.lbr_to = MSR_ARCH_LBR_TO_0; in intel_pmu_arch_lbr_init()
1806 x86_pmu.lbr_info = MSR_ARCH_LBR_INFO_0; in intel_pmu_arch_lbr_init()
1809 if (!x86_pmu.lbr_cpl || in intel_pmu_arch_lbr_init()
1810 !x86_pmu.lbr_filter || in intel_pmu_arch_lbr_init()
1811 !x86_pmu.lbr_call_stack) in intel_pmu_arch_lbr_init()
1814 if (!x86_pmu.lbr_cpl) { in intel_pmu_arch_lbr_init()
1817 } else if (!x86_pmu.lbr_filter) { in intel_pmu_arch_lbr_init()
1827 x86_pmu.lbr_ctl_mask = ARCH_LBR_CTL_MASK; in intel_pmu_arch_lbr_init()
1828 x86_pmu.lbr_ctl_map = arch_lbr_ctl_map; in intel_pmu_arch_lbr_init()
1830 if (!x86_pmu.lbr_cpl && !x86_pmu.lbr_filter) in intel_pmu_arch_lbr_init()
1831 x86_pmu.lbr_ctl_map = NULL; in intel_pmu_arch_lbr_init()
1833 x86_pmu.lbr_reset = intel_pmu_arch_lbr_reset; in intel_pmu_arch_lbr_init()
1835 x86_pmu.lbr_save = intel_pmu_arch_lbr_xsaves; in intel_pmu_arch_lbr_init()
1836 x86_pmu.lbr_restore = intel_pmu_arch_lbr_xrstors; in intel_pmu_arch_lbr_init()
1837 x86_pmu.lbr_read = intel_pmu_arch_lbr_read_xsave; in intel_pmu_arch_lbr_init()
1840 x86_pmu.lbr_save = intel_pmu_arch_lbr_save; in intel_pmu_arch_lbr_init()
1841 x86_pmu.lbr_restore = intel_pmu_arch_lbr_restore; in intel_pmu_arch_lbr_init()
1842 x86_pmu.lbr_read = intel_pmu_arch_lbr_read; in intel_pmu_arch_lbr_init()
1862 int lbr_fmt = x86_pmu.intel_cap.lbr_format; in x86_perf_get_lbr()
1864 lbr->nr = x86_pmu.lbr_nr; in x86_perf_get_lbr()
1865 lbr->from = x86_pmu.lbr_from; in x86_perf_get_lbr()
1866 lbr->to = x86_pmu.lbr_to; in x86_perf_get_lbr()
1867 lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0; in x86_perf_get_lbr()