48 static inline bool clk_master_ready(struct clk_master *master)  in clk_master_ready()  argument
50 	unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;  in clk_master_ready()
53 	regmap_read(master->regmap, AT91_PMC_SR, &status);  in clk_master_ready()
60 	struct clk_master *master = to_clk_master(hw);  in clk_master_prepare()  local
62 	while (!clk_master_ready(master))  in clk_master_prepare()
70 	struct clk_master *master = to_clk_master(hw);  in clk_master_is_prepared()  local
72 	return clk_master_ready(master);  in clk_master_is_prepared()
81 	struct clk_master *master = to_clk_master(hw);  in clk_master_recalc_rate()  local
82 	const struct clk_master_layout *layout = master->layout;  in clk_master_recalc_rate()
84 						master->characteristics;  in clk_master_recalc_rate()
87 	regmap_read(master->regmap, master->layout->offset, &mckr);  in clk_master_recalc_rate()
110 	struct clk_master *master = to_clk_master(hw);  in clk_master_get_parent()  local
113 	regmap_read(master->regmap, master->layout->offset, &mckr);  in clk_master_get_parent()
132 	struct clk_master *master;  in at91_clk_register_master()  local
140 	master = kzalloc(sizeof(*master), GFP_KERNEL);  in at91_clk_register_master()
141 	if (!master)  in at91_clk_register_master()
150 	master->hw.init = &init;  in at91_clk_register_master()
151 	master->layout = layout;  in at91_clk_register_master()
152 	master->characteristics = characteristics;  in at91_clk_register_master()
153 	master->regmap = regmap;  in at91_clk_register_master()
155 	hw = &master->hw;  in at91_clk_register_master()
156 	ret = clk_hw_register(NULL, &master->hw);  in at91_clk_register_master()
158 		kfree(master);  in at91_clk_register_master()
169 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_recalc_rate()  local
171 	return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));  in clk_sama7g5_master_recalc_rate()
201 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_determine_rate()  local
231 	if (master->chg_pid < 0)  in clk_sama7g5_master_determine_rate()
234 	parent = clk_hw_get_parent_by_index(hw, master->chg_pid);  in clk_sama7g5_master_determine_rate()
270 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_get_parent()  local
274 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_get_parent()
275 	index = clk_mux_val_to_index(&master->hw, master->mux_table, 0,  in clk_sama7g5_master_get_parent()
276 				     master->parent);  in clk_sama7g5_master_get_parent()
277 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_get_parent()
284 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_set_parent()  local
290 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_set_parent()
291 	master->parent = clk_mux_index_to_val(master->mux_table, 0, index);  in clk_sama7g5_master_set_parent()
292 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_set_parent()
299 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_enable()  local
303 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_enable()
305 	regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));  in clk_sama7g5_master_enable()
306 	regmap_read(master->regmap, PMC_MCR, &val);  in clk_sama7g5_master_enable()
307 	regmap_update_bits(master->regmap, PMC_MCR,  in clk_sama7g5_master_enable()
310 			   PMC_MCR_EN | (master->parent << PMC_MCR_CSS_SHIFT) |  in clk_sama7g5_master_enable()
311 			   (master->div << MASTER_DIV_SHIFT) |  in clk_sama7g5_master_enable()
312 			   PMC_MCR_CMD | PMC_MCR_ID(master->id));  in clk_sama7g5_master_enable()
317 	while ((cparent != master->parent) && !clk_master_ready(master))  in clk_sama7g5_master_enable()
320 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_enable()
327 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_disable()  local
330 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_disable()
332 	regmap_write(master->regmap, PMC_MCR, master->id);  in clk_sama7g5_master_disable()
333 	regmap_update_bits(master->regmap, PMC_MCR,  in clk_sama7g5_master_disable()
335 			   PMC_MCR_CMD | PMC_MCR_ID(master->id));  in clk_sama7g5_master_disable()
337 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_disable()
342 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_is_enabled()  local
346 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_is_enabled()
348 	regmap_write(master->regmap, PMC_MCR, master->id);  in clk_sama7g5_master_is_enabled()
349 	regmap_read(master->regmap, PMC_MCR, &val);  in clk_sama7g5_master_is_enabled()
351 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_is_enabled()
359 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_set_rate()  local
371 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_set_rate()
372 	master->div = div;  in clk_sama7g5_master_set_rate()
373 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_set_rate()
397 	struct clk_master *master;  in at91_clk_sama7g5_register_master()  local
408 	master = kzalloc(sizeof(*master), GFP_KERNEL);  in at91_clk_sama7g5_register_master()
409 	if (!master)  in at91_clk_sama7g5_register_master()
422 	master->hw.init = &init;  in at91_clk_sama7g5_register_master()
423 	master->regmap = regmap;  in at91_clk_sama7g5_register_master()
424 	master->id = id;  in at91_clk_sama7g5_register_master()
425 	master->chg_pid = chg_pid;  in at91_clk_sama7g5_register_master()
426 	master->lock = lock;  in at91_clk_sama7g5_register_master()
427 	master->mux_table = mux_table;  in at91_clk_sama7g5_register_master()
429 	spin_lock_irqsave(master->lock, flags);  in at91_clk_sama7g5_register_master()
430 	regmap_write(master->regmap, PMC_MCR, master->id);  in at91_clk_sama7g5_register_master()
431 	regmap_read(master->regmap, PMC_MCR, &val);  in at91_clk_sama7g5_register_master()
432 	master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;  in at91_clk_sama7g5_register_master()
433 	master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT;  in at91_clk_sama7g5_register_master()
434 	spin_unlock_irqrestore(master->lock, flags);  in at91_clk_sama7g5_register_master()
436 	hw = &master->hw;  in at91_clk_sama7g5_register_master()
437 	ret = clk_hw_register(NULL, &master->hw);  in at91_clk_sama7g5_register_master()
439 		kfree(master);  in at91_clk_sama7g5_register_master()