Lines Matching refs:divider
81 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_recalc_rate() local
83 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
84 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
99 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_recalc_rate()
103 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in zynqmp_clk_divider_recalc_rate()
124 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_round_rate() local
126 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate()
127 u32 div_type = divider->div_type; in zynqmp_clk_divider_round_rate()
133 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in zynqmp_clk_divider_round_rate()
144 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_round_rate()
150 width = fls(divider->max_div); in zynqmp_clk_divider_round_rate()
152 rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags); in zynqmp_clk_divider_round_rate()
154 if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate)) in zynqmp_clk_divider_round_rate()
171 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_set_rate() local
173 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_set_rate()
174 u32 div_type = divider->div_type; in zynqmp_clk_divider_set_rate()
178 value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); in zynqmp_clk_divider_set_rate()
187 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_set_rate()