61 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);  in npcm7xx_timer_resume()
63 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);  in npcm7xx_timer_resume()
73 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);  in npcm7xx_timer_shutdown()
75 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);  in npcm7xx_timer_shutdown()
85 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);  in npcm7xx_timer_oneshot()
88 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);  in npcm7xx_timer_oneshot()
98 	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);  in npcm7xx_timer_periodic()
100 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);  in npcm7xx_timer_periodic()
103 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);  in npcm7xx_timer_periodic()
114 	writel(evt, timer_of_base(to) + NPCM7XX_REG_TICR0);  in npcm7xx_clockevent_set_next_event()
115 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);  in npcm7xx_clockevent_set_next_event()
117 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);  in npcm7xx_clockevent_set_next_event()
127 	writel(NPCM7XX_T0_CLR_INT, timer_of_base(to) + NPCM7XX_REG_TISR);  in npcm7xx_timer0_interrupt()
158 		timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR0);  in npcm7xx_clockevents_init()
161 		timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TISR);  in npcm7xx_clockevents_init()
174 		timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);  in npcm7xx_clocksource_init()
176 		timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TICR1);  in npcm7xx_clocksource_init()
178 	val = readl(timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);  in npcm7xx_clocksource_init()
180 	writel(val, timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);  in npcm7xx_clocksource_init()
182 	clocksource_mmio_init(timer_of_base(&npcm7xx_to) +  in npcm7xx_clocksource_init()
206 		timer_of_base(&npcm7xx_to), timer_of_irq(&npcm7xx_to));  in npcm7xx_timer_init()