Lines Matching refs:offset
43 u64 offset; in nitrox_config_emu_unit() local
57 offset = EMU_WD_INT_ENA_W1SX(i); in nitrox_config_emu_unit()
58 nitrox_write_csr(ndev, offset, emu_wd_int.value); in nitrox_config_emu_unit()
59 offset = EMU_GE_INT_ENA_W1SX(i); in nitrox_config_emu_unit()
60 nitrox_write_csr(ndev, offset, emu_ge_int.value); in nitrox_config_emu_unit()
69 u64 offset; in reset_pkt_input_ring() local
72 offset = NPS_PKT_IN_INSTR_CTLX(ring); in reset_pkt_input_ring()
73 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
75 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in reset_pkt_input_ring()
80 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
87 offset = NPS_PKT_IN_DONE_CNTSX(ring); in reset_pkt_input_ring()
88 pkt_in_cnts.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
89 nitrox_write_csr(ndev, offset, pkt_in_cnts.value); in reset_pkt_input_ring()
97 u64 offset; in enable_pkt_input_ring() local
100 offset = NPS_PKT_IN_INSTR_CTLX(ring); in enable_pkt_input_ring()
101 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_input_ring()
104 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in enable_pkt_input_ring()
108 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_input_ring()
127 u64 offset; in nitrox_config_pkt_input_rings() local
136 offset = NPS_PKT_IN_INSTR_BADDRX(i); in nitrox_config_pkt_input_rings()
137 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_pkt_input_rings()
140 offset = NPS_PKT_IN_INSTR_RSIZEX(i); in nitrox_config_pkt_input_rings()
143 nitrox_write_csr(ndev, offset, pkt_in_rsize.value); in nitrox_config_pkt_input_rings()
146 offset = NPS_PKT_IN_INT_LEVELSX(i); in nitrox_config_pkt_input_rings()
147 nitrox_write_csr(ndev, offset, 0xffffffff); in nitrox_config_pkt_input_rings()
150 offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(i); in nitrox_config_pkt_input_rings()
153 nitrox_write_csr(ndev, offset, pkt_in_dbell.value); in nitrox_config_pkt_input_rings()
165 u64 offset; in reset_pkt_solicit_port() local
168 offset = NPS_PKT_SLC_CTLX(port); in reset_pkt_solicit_port()
169 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
171 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in reset_pkt_solicit_port()
177 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
184 offset = NPS_PKT_SLC_CNTSX(port); in reset_pkt_solicit_port()
185 pkt_slc_cnts.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
186 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value); in reset_pkt_solicit_port()
194 u64 offset; in enable_pkt_solicit_port() local
196 offset = NPS_PKT_SLC_CTLX(port); in enable_pkt_solicit_port()
206 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in enable_pkt_solicit_port()
210 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_solicit_port()
220 u64 offset; in config_pkt_solicit_port() local
225 offset = NPS_PKT_SLC_INT_LEVELSX(port); in config_pkt_solicit_port()
229 nitrox_write_csr(ndev, offset, pkt_slc_int.value); in config_pkt_solicit_port()
314 u64 offset; in reset_aqm_ring() local
317 offset = AQMQ_ENX(ring); in reset_aqm_ring()
320 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in reset_aqm_ring()
324 offset = AQMQ_ACTIVITY_STATX(ring); in reset_aqm_ring()
326 activity_stat.value = nitrox_read_csr(ndev, offset); in reset_aqm_ring()
333 offset = AQMQ_CMP_CNTX(ring); in reset_aqm_ring()
334 cmp_cnt.value = nitrox_read_csr(ndev, offset); in reset_aqm_ring()
335 nitrox_write_csr(ndev, offset, cmp_cnt.value); in reset_aqm_ring()
342 u64 offset; in enable_aqm_ring() local
344 offset = AQMQ_ENX(ring); in enable_aqm_ring()
347 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in enable_aqm_ring()
360 u64 offset; in nitrox_config_aqm_rings() local
366 offset = AQMQ_DRBLX(ring); in nitrox_config_aqm_rings()
369 nitrox_write_csr(ndev, offset, drbl.value); in nitrox_config_aqm_rings()
374 offset = AQMQ_NXT_CMDX(ring); in nitrox_config_aqm_rings()
375 nitrox_write_csr(ndev, offset, 0ULL); in nitrox_config_aqm_rings()
378 offset = AQMQ_BADRX(ring); in nitrox_config_aqm_rings()
379 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_aqm_rings()
382 offset = AQMQ_QSZX(ring); in nitrox_config_aqm_rings()
385 nitrox_write_csr(ndev, offset, qsize.value); in nitrox_config_aqm_rings()
388 offset = AQMQ_CMP_THRX(ring); in nitrox_config_aqm_rings()
391 nitrox_write_csr(ndev, offset, cmp_thr.value); in nitrox_config_aqm_rings()
442 u64 offset; in nitrox_config_rand_unit() local
444 offset = EFL_RNM_CTL_STATUS; in nitrox_config_rand_unit()
445 efl_rnm_ctl.value = nitrox_read_csr(ndev, offset); in nitrox_config_rand_unit()
448 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value); in nitrox_config_rand_unit()
457 u64 offset; in nitrox_config_efl_unit() local
460 offset = EFL_CORE_INT_ENA_W1SX(i); in nitrox_config_efl_unit()
465 nitrox_write_csr(ndev, offset, efl_core_int.value); in nitrox_config_efl_unit()
467 offset = EFL_CORE_VF_ERR_INT0_ENA_W1SX(i); in nitrox_config_efl_unit()
468 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
469 offset = EFL_CORE_VF_ERR_INT1_ENA_W1SX(i); in nitrox_config_efl_unit()
470 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
478 u64 offset; in nitrox_config_bmi_unit() local
481 offset = BMI_CTL; in nitrox_config_bmi_unit()
482 bmi_ctl.value = nitrox_read_csr(ndev, offset); in nitrox_config_bmi_unit()
486 nitrox_write_csr(ndev, offset, bmi_ctl.value); in nitrox_config_bmi_unit()
489 offset = BMI_INT_ENA_W1S; in nitrox_config_bmi_unit()
494 nitrox_write_csr(ndev, offset, bmi_int_ena.value); in nitrox_config_bmi_unit()
500 u64 offset; in nitrox_config_bmo_unit() local
503 offset = BMO_CTL2; in nitrox_config_bmo_unit()
504 bmo_ctl2.value = nitrox_read_csr(ndev, offset); in nitrox_config_bmo_unit()
506 nitrox_write_csr(ndev, offset, bmo_ctl2.value); in nitrox_config_bmo_unit()
514 u64 offset; in invalidate_lbc() local
517 offset = LBC_INVAL_CTL; in invalidate_lbc()
518 lbc_ctl.value = nitrox_read_csr(ndev, offset); in invalidate_lbc()
520 nitrox_write_csr(ndev, offset, lbc_ctl.value); in invalidate_lbc()
522 offset = LBC_INVAL_STATUS; in invalidate_lbc()
524 lbc_stat.value = nitrox_read_csr(ndev, offset); in invalidate_lbc()
534 u64 offset; in nitrox_config_lbc_unit() local
539 offset = LBC_INT_ENA_W1S; in nitrox_config_lbc_unit()
545 nitrox_write_csr(ndev, offset, lbc_int_ena.value); in nitrox_config_lbc_unit()
547 offset = LBC_PLM_VF1_64_INT_ENA_W1S; in nitrox_config_lbc_unit()
548 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
549 offset = LBC_PLM_VF65_128_INT_ENA_W1S; in nitrox_config_lbc_unit()
550 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
552 offset = LBC_ELM_VF1_64_INT_ENA_W1S; in nitrox_config_lbc_unit()
553 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
554 offset = LBC_ELM_VF65_128_INT_ENA_W1S; in nitrox_config_lbc_unit()
555 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
614 u64 offset; in nitrox_get_hwinfo() local
617 offset = RST_BOOT; in nitrox_get_hwinfo()
618 rst_boot.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()
622 offset = EMU_FUSE_MAPX(i); in nitrox_get_hwinfo()
623 emu_fuse.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()
632 offset = FUS_DAT1; in nitrox_get_hwinfo()
633 fus_dat1.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()