Lines Matching defs:cryp_register

82 struct cryp_register {  struct
83 	u32 cr;			/* Configuration register   */
84 	u32 sr;			/* Status register          */
85 	u32 din;		/* Data input register      */
86 	u32 din_size;		/* Data input size register */
87 	u32 dout;		/* Data output register     */
88 	u32 dout_size;		/* Data output size register */
89 	u32 dmacr;		/* Dma control register     */
90 	u32 imsc;		/* Interrupt mask set/clear register */
91 	u32 ris;		/* Raw interrupt status             */
92 	u32 mis;		/* Masked interrupt statu register  */
94 	u32 key_1_l;		/*Key register 1 L */
95 	u32 key_1_r;		/*Key register 1 R */
96 	u32 key_2_l;		/*Key register 2 L */
97 	u32 key_2_r;		/*Key register 2 R */
98 	u32 key_3_l;		/*Key register 3 L */
99 	u32 key_3_r;		/*Key register 3 R */
100 	u32 key_4_l;		/*Key register 4 L */
101 	u32 key_4_r;		/*Key register 4 R */
103 	u32 init_vect_0_l;	/*init vector 0 L */
104 	u32 init_vect_0_r;	/*init vector 0 R */
105 	u32 init_vect_1_l;	/*init vector 1 L */
106 	u32 init_vect_1_r;	/*init vector 1 R */
108 	u32 cryp_unused1[(0x80 - 0x58) / sizeof(u32)];	/* unused registers */
109 	u32 itcr;		/*Integration test control register */
110 	u32 itip;		/*Integration test input register */
111 	u32 itop;		/*Integration test output register */
112 	u32 cryp_unused2[(0xFE0 - 0x8C) / sizeof(u32)];	/* unused registers */
114 	u32 periphId0;		/* FE0  CRYP Peripheral Identication Register */
115 	u32 periphId1;		/* FE4 */
116 	u32 periphId2;		/* FE8 */
117 	u32 periphId3;		/* FEC */
119 	u32 pcellId0;		/* FF0  CRYP PCell Identication Register */
120 	u32 pcellId1;		/* FF4 */
121 	u32 pcellId2;		/* FF8 */
122 	u32 pcellId3;		/* FFC */