226 	u16 mask;  in vr41xx_set_irq_trigger()  local
229 		mask = 1 << pin;  in vr41xx_set_irq_trigger()
231 			giu_set(GIUINTTYPL, mask);  in vr41xx_set_irq_trigger()
233 				giu_set(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
235 				giu_clear(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
239 					giu_set(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
240 					giu_clear(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
243 					giu_clear(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
244 					giu_set(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
247 					giu_set(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
248 					giu_set(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
256 			giu_clear(GIUINTTYPL, mask);  in vr41xx_set_irq_trigger()
257 			giu_clear(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
262 		giu_write(GIUINTSTATL, mask);  in vr41xx_set_irq_trigger()
264 		mask = 1 << (pin - GIUINT_HIGH_OFFSET);  in vr41xx_set_irq_trigger()
266 			giu_set(GIUINTTYPH, mask);  in vr41xx_set_irq_trigger()
268 				giu_set(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
270 				giu_clear(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
274 					giu_set(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
275 					giu_clear(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
278 					giu_clear(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
279 					giu_set(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
282 					giu_set(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
283 					giu_set(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
291 			giu_clear(GIUINTTYPH, mask);  in vr41xx_set_irq_trigger()
292 			giu_clear(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
297 		giu_write(GIUINTSTATH, mask);  in vr41xx_set_irq_trigger()
304 	u16 mask;  in vr41xx_set_irq_level()  local
307 		mask = 1 << pin;  in vr41xx_set_irq_level()
309 			giu_set(GIUINTALSELL, mask);  in vr41xx_set_irq_level()
311 			giu_clear(GIUINTALSELL, mask);  in vr41xx_set_irq_level()
312 		giu_write(GIUINTSTATL, mask);  in vr41xx_set_irq_level()
314 		mask = 1 << (pin - GIUINT_HIGH_OFFSET);  in vr41xx_set_irq_level()
316 			giu_set(GIUINTALSELH, mask);  in vr41xx_set_irq_level()
318 			giu_clear(GIUINTALSELH, mask);  in vr41xx_set_irq_level()
319 		giu_write(GIUINTSTATH, mask);  in vr41xx_set_irq_level()
326 	u16 offset, mask, reg;  in giu_set_direction()  local
334 		mask = 1 << pin;  in giu_set_direction()
337 		mask = 1 << (pin - 16);  in giu_set_direction()
341 			mask = 1 << (pin - 32);  in giu_set_direction()
346 				mask = PIOEN0;  in giu_set_direction()
350 				mask = PIOEN1;  in giu_set_direction()
362 		reg |= mask;  in giu_set_direction()
364 		reg &= ~mask;  in giu_set_direction()
374 	u16 reg, mask;  in vr41xx_gpio_get()  local
381 		mask = 1 << pin;  in vr41xx_gpio_get()
384 		mask = 1 << (pin - 16);  in vr41xx_gpio_get()
387 		mask = 1 << (pin - 32);  in vr41xx_gpio_get()
390 		mask = 1 << (pin - 48);  in vr41xx_gpio_get()
393 	if (reg & mask)  in vr41xx_gpio_get()
402 	u16 offset, mask, reg;  in vr41xx_gpio_set()  local
410 		mask = 1 << pin;  in vr41xx_gpio_set()
413 		mask = 1 << (pin - 16);  in vr41xx_gpio_set()
416 		mask = 1 << (pin - 32);  in vr41xx_gpio_set()
419 		mask = 1 << (pin - 48);  in vr41xx_gpio_set()
426 		reg |= mask;  in vr41xx_gpio_set()
428 		reg &= ~mask;  in vr41xx_gpio_set()