Lines Matching refs:gpu
103 static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq) in _get_mvolts() argument
105 struct drm_device *dev = gpu->dev; in _get_mvolts()
122 static void a530_lm_setup(struct msm_gpu *gpu) in a530_lm_setup() argument
124 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a530_lm_setup()
130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
134 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a530_lm_setup()
135 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a530_lm_setup()
136 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a530_lm_setup()
139 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a530_lm_setup()
141 gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage); in a530_lm_setup()
144 gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000); in a530_lm_setup()
146 gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF); in a530_lm_setup()
147 gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x00201FF1); in a530_lm_setup()
150 gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF); in a530_lm_setup()
151 gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x201FF1); in a530_lm_setup()
153 gpu_write(gpu, AGC_MSG_STATE, 1); in a530_lm_setup()
154 gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID); in a530_lm_setup()
157 gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448); in a530_lm_setup()
158 gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1); in a530_lm_setup()
164 gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate)); in a530_lm_setup()
165 gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000); in a530_lm_setup()
167 gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, 4 * sizeof(uint32_t)); in a530_lm_setup()
168 gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE); in a530_lm_setup()
175 static void a540_lm_setup(struct msm_gpu *gpu) in a540_lm_setup() argument
177 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a540_lm_setup()
188 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a540_lm_setup()
191 gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000); in a540_lm_setup()
193 gpu_write(gpu, AGC_MSG_STATE, 0x80000001); in a540_lm_setup()
194 gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID); in a540_lm_setup()
196 gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448); in a540_lm_setup()
197 gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1); in a540_lm_setup()
199 gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate)); in a540_lm_setup()
200 gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000); in a540_lm_setup()
202 gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LM_CONFIG), config); in a540_lm_setup()
203 gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LEVEL_CONFIG), LEVEL_CONFIG); in a540_lm_setup()
204 gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, in a540_lm_setup()
207 gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE); in a540_lm_setup()
211 static void a5xx_pc_init(struct msm_gpu *gpu) in a5xx_pc_init() argument
213 gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL, 0x7F); in a5xx_pc_init()
214 gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_BINNING_CTRL, 0); in a5xx_pc_init()
215 gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST, 0xA0080); in a5xx_pc_init()
216 gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY, 0x600040); in a5xx_pc_init()
220 static int a5xx_gpmu_init(struct msm_gpu *gpu) in a5xx_gpmu_init() argument
222 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_gpmu_init()
224 struct msm_ringbuffer *ring = gpu->rb[0]; in a5xx_gpmu_init()
243 a5xx_flush(gpu, ring, true); in a5xx_gpmu_init()
245 if (!a5xx_idle(gpu, ring)) { in a5xx_gpmu_init()
247 gpu->name); in a5xx_gpmu_init()
252 gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014); in a5xx_gpmu_init()
255 gpu_write(gpu, REG_A5XX_GPMU_CM3_SYSRESET, 0x0); in a5xx_gpmu_init()
261 if (spin_usecs(gpu, 25, REG_A5XX_GPMU_GENERAL_0, 0xFFFFFFFF, in a5xx_gpmu_init()
264 gpu->name); in a5xx_gpmu_init()
267 u32 val = gpu_read(gpu, REG_A5XX_GPMU_GENERAL_1); in a5xx_gpmu_init()
271 gpu->name, val); in a5xx_gpmu_init()
278 static void a5xx_lm_enable(struct msm_gpu *gpu) in a5xx_lm_enable() argument
280 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_lm_enable()
286 gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0); in a5xx_lm_enable()
287 gpu_write(gpu, REG_A5XX_GDPM_INT_EN, 0x0A); in a5xx_lm_enable()
288 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK, 0x01); in a5xx_lm_enable()
289 gpu_write(gpu, REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK, 0x50000); in a5xx_lm_enable()
290 gpu_write(gpu, REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL, 0x30000); in a5xx_lm_enable()
292 gpu_write(gpu, REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL, 0x011); in a5xx_lm_enable()
295 int a5xx_power_init(struct msm_gpu *gpu) in a5xx_power_init() argument
297 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_power_init()
306 a530_lm_setup(gpu); in a5xx_power_init()
308 a540_lm_setup(gpu); in a5xx_power_init()
311 a5xx_pc_init(gpu); in a5xx_power_init()
314 ret = a5xx_gpmu_init(gpu); in a5xx_power_init()
319 a5xx_lm_enable(gpu); in a5xx_power_init()
324 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) in a5xx_gpmu_ucode_init() argument
326 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_gpmu_ucode_init()
328 struct drm_device *drm = gpu->dev; in a5xx_gpmu_ucode_init()
366 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, in a5xx_gpmu_ucode_init()