402 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);  in nv50_outp_atomic_fix_depth()  local
404 	struct drm_display_mode *mode = &asyh->state.adjusted_mode;  in nv50_outp_atomic_fix_depth()
412 		asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);  in nv50_outp_atomic_fix_depth()
415 		while (asyh->or.bpc > 6) {  in nv50_outp_atomic_fix_depth()
416 			mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);  in nv50_outp_atomic_fix_depth()
420 			asyh->or.bpc -= 2;  in nv50_outp_atomic_fix_depth()
435 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);  in nv50_outp_atomic_check()  local
444 		asyh->or.bpc = connector->display_info.bpc;  in nv50_outp_atomic_check()
506 	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);  in nv50_dac_enable()  local
524 	core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);  in nv50_dac_enable()
525 	asyh->or.depth = 0;  in nv50_dac_enable()
1043 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);  in nv50_msto_atomic_check()  local
1063 		asyh->or.bpc = connector->display_info.bpc;  in nv50_msto_atomic_check()
1064 		asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,  in nv50_msto_atomic_check()
1069 					      asyh->dp.pbn, 0);  in nv50_msto_atomic_check()
1073 	asyh->dp.tu = slots;  in nv50_msto_atomic_check()
1629 		struct nv50_head_atom *asyh, u8 proto, u8 depth)  in nv50_sor_update()  argument
1634 	if (!asyh) {  in nv50_sor_update()
1641 		asyh->or.depth = depth;  in nv50_sor_update()
1644 	core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);  in nv50_sor_update()
1684 	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);  in nv50_sor_enable()  local
1685 	struct drm_display_mode *mode = &asyh->state.adjusted_mode;  in nv50_sor_enable()
1758 			if (asyh->or.bpc == 8)  in nv50_sor_enable()
1765 		depth = nv50_dp_bpc_to_depth(asyh->or.bpc);  in nv50_sor_enable()
1779 	nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);  in nv50_sor_enable()
1923 	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);  in nv50_pior_enable()  local
1937 	switch (asyh->or.bpc) {  in nv50_pior_enable()
1938 	case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;  in nv50_pior_enable()
1939 	case  8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;  in nv50_pior_enable()
1940 	case  6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;  in nv50_pior_enable()
1941 	default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;  in nv50_pior_enable()
1954 	core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);  in nv50_pior_enable()
2110 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_commit_tail()  local
2114 			  asyh->clr.mask, asyh->set.mask);  in nv50_disp_atomic_commit_tail()
2121 		if (asyh->clr.mask) {  in nv50_disp_atomic_commit_tail()
2122 			nv50_head_flush_clr(head, asyh, atom->flush_disable);  in nv50_disp_atomic_commit_tail()
2201 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_commit_tail()  local
2205 			  asyh->set.mask, asyh->clr.mask);  in nv50_disp_atomic_commit_tail()
2207 		if (asyh->set.mask) {  in nv50_disp_atomic_commit_tail()
2208 			nv50_head_flush_set(head, asyh);  in nv50_disp_atomic_commit_tail()
2252 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_commit_tail()  local
2256 			  asyh->set.mask, asyh->clr.mask);  in nv50_disp_atomic_commit_tail()
2258 		if (asyh->set.mask) {  in nv50_disp_atomic_commit_tail()
2259 			nv50_head_flush_set_wndw(head, asyh);  in nv50_disp_atomic_commit_tail()
2487 	struct nv50_head_atom *asyh;  in nv50_disp_atomic_check()  local
2498 			asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_check()
2499 			core->func->head->static_wndw_map(head, asyh);  in nv50_disp_atomic_check()