1782 	u32 idx_value;  in evergreen_packet3_check()  local
1787 	idx_value = radeon_get_ib_value(p, idx);  in evergreen_packet3_check()
1820 			 (idx_value & 0xfffffff0) +  in evergreen_packet3_check()
1866 			 idx_value +  in evergreen_packet3_check()
1901 			 idx_value +  in evergreen_packet3_check()
2012 		if (idx_value != 1) {  in evergreen_packet3_check()
2045 		if (idx_value + size > track->indirect_draw_buffer_size) {  in evergreen_packet3_check()
2047 				idx_value, size, track->indirect_draw_buffer_size);  in evergreen_packet3_check()
2079 		ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff);  in evergreen_packet3_check()
2092 		if (idx_value & 0x10) {  in evergreen_packet3_check()
2107 		} else if (idx_value & 0x100) {  in evergreen_packet3_check()
2301 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;  in evergreen_packet3_check()
2318 		start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;  in evergreen_packet3_check()
2339 		start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;  in evergreen_packet3_check()
2442 		start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;  in evergreen_packet3_check()
2452 		start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;  in evergreen_packet3_check()
2462 		start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;  in evergreen_packet3_check()
2476 		start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;  in evergreen_packet3_check()
2491 		if (idx_value & 0x1) {  in evergreen_packet3_check()
2510 		if (((idx_value >> 1) & 0x3) == 2) {  in evergreen_packet3_check()
2563 		if (idx_value & 0x1) {  in evergreen_packet3_check()
2590 		if (idx_value & 0x2) {  in evergreen_packet3_check()
2632 		areg = idx_value >> 16;  in evergreen_packet3_check()
2639 		source_sel = G_PACKET3_SET_APPEND_CNT_SRC_SELECT(idx_value);  in evergreen_packet3_check()
3352 	u32 idx_value = ib[idx];  in evergreen_vm_packet3_check()  local
3360 		if (idx_value != 1) {  in evergreen_vm_packet3_check()
3408 		if (idx_value & 0x100) {  in evergreen_vm_packet3_check()
3415 		if (idx_value & 0x2) {  in evergreen_vm_packet3_check()
3422 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;  in evergreen_vm_packet3_check()
3454 				start_reg = idx_value << 2;  in evergreen_vm_packet3_check()
3507 		areg = idx_value >> 16;  in evergreen_vm_packet3_check()