98 	u32 ctl_val[smc_max];			/* control settings */  member
280 	u32 ctl = chip->ctl_val[smc_base];  in aspeed_smc_start_user()
300 	u32 ctl = chip->ctl_val[smc_read];  in aspeed_smc_stop_user()
642 	chip->ctl_val[smc_base] |= CONTROL_IO_ADDRESS_4B;  in aspeed_smc_chip_set_4b_spi_2400()
643 	chip->ctl_val[smc_read] |= CONTROL_IO_ADDRESS_4B;  in aspeed_smc_chip_set_4b_spi_2400()
687 	chip->ctl_val[smc_base] = base_reg;  in aspeed_smc_chip_setup_init()
696 		chip->ctl_val[smc_read] = reg;  in aspeed_smc_chip_setup_init()
698 		chip->ctl_val[smc_read] = chip->ctl_val[smc_base] |  in aspeed_smc_chip_setup_init()
702 		chip->ctl_val[smc_read]);  in aspeed_smc_chip_setup_init()
721 	chip->ctl_val[smc_write] = chip->ctl_val[smc_base] |  in aspeed_smc_chip_setup_finish()
726 		chip->ctl_val[smc_write]);  in aspeed_smc_chip_setup_finish()
742 	chip->ctl_val[smc_read] |= cmd |  in aspeed_smc_chip_setup_finish()
746 		chip->ctl_val[smc_read]);  in aspeed_smc_chip_setup_finish()