Lines Matching refs:reg
20 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_read() argument
25 return mv88e6xxx_read(chip, addr, reg, val); in mv88e6xxx_port_read()
28 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, in mv88e6xxx_port_write() argument
33 return mv88e6xxx_write(chip, addr, reg, val); in mv88e6xxx_port_write()
44 u16 reg; in mv88e6185_port_set_pause() local
47 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6185_port_set_pause()
52 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; in mv88e6185_port_set_pause()
54 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; in mv88e6185_port_set_pause()
56 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); in mv88e6185_port_set_pause()
71 u16 reg; in mv88e6xxx_port_set_rgmii_delay() local
74 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_rgmii_delay()
78 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | in mv88e6xxx_port_set_rgmii_delay()
83 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; in mv88e6xxx_port_set_rgmii_delay()
86 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; in mv88e6xxx_port_set_rgmii_delay()
89 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | in mv88e6xxx_port_set_rgmii_delay()
98 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_rgmii_delay()
103 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", in mv88e6xxx_port_set_rgmii_delay()
104 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); in mv88e6xxx_port_set_rgmii_delay()
129 u16 reg; in mv88e6xxx_port_set_link() local
132 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_link()
136 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | in mv88e6xxx_port_set_link()
141 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; in mv88e6xxx_port_set_link()
144 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | in mv88e6xxx_port_set_link()
154 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_link()
159 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", in mv88e6xxx_port_set_link()
160 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); in mv88e6xxx_port_set_link()
169 u16 reg, ctrl; in mv88e6xxx_port_set_speed_duplex() local
220 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); in mv88e6xxx_port_set_speed_duplex()
224 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | in mv88e6xxx_port_set_speed_duplex()
229 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; in mv88e6xxx_port_set_speed_duplex()
231 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; in mv88e6xxx_port_set_speed_duplex()
235 reg |= ctrl; in mv88e6xxx_port_set_speed_duplex()
237 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); in mv88e6xxx_port_set_speed_duplex()
246 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", in mv88e6xxx_port_set_speed_duplex()
247 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); in mv88e6xxx_port_set_speed_duplex()
398 u16 reg; in mv88e6xxx_port_set_cmode() local
448 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6xxx_port_set_cmode()
452 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; in mv88e6xxx_port_set_cmode()
453 reg |= cmode; in mv88e6xxx_port_set_cmode()
455 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); in mv88e6xxx_port_set_cmode()
512 u16 reg, bits; in mv88e6341_port_set_cmode_writable() local
519 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); in mv88e6341_port_set_cmode_writable()
526 if ((reg & bits) == bits) in mv88e6341_port_set_cmode_writable()
529 reg |= bits; in mv88e6341_port_set_cmode_writable()
530 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); in mv88e6341_port_set_cmode_writable()
562 u16 reg; in mv88e6185_port_get_cmode() local
564 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6185_port_get_cmode()
568 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; in mv88e6185_port_get_cmode()
576 u16 reg; in mv88e6352_port_get_cmode() local
578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); in mv88e6352_port_get_cmode()
582 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; in mv88e6352_port_get_cmode()
627 u16 reg; in mv88e6xxx_port_set_state() local
630 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_state()
634 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; in mv88e6xxx_port_set_state()
654 reg |= state; in mv88e6xxx_port_set_state()
656 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_state()
670 u16 reg; in mv88e6xxx_port_set_egress_mode() local
672 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6xxx_port_set_egress_mode()
676 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; in mv88e6xxx_port_set_egress_mode()
680 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; in mv88e6xxx_port_set_egress_mode()
683 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; in mv88e6xxx_port_set_egress_mode()
686 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; in mv88e6xxx_port_set_egress_mode()
689 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; in mv88e6xxx_port_set_egress_mode()
695 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6xxx_port_set_egress_mode()
702 u16 reg; in mv88e6085_port_set_frame_mode() local
704 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6085_port_set_frame_mode()
708 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; in mv88e6085_port_set_frame_mode()
712 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; in mv88e6085_port_set_frame_mode()
715 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; in mv88e6085_port_set_frame_mode()
721 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6085_port_set_frame_mode()
728 u16 reg; in mv88e6351_port_set_frame_mode() local
730 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6351_port_set_frame_mode()
734 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; in mv88e6351_port_set_frame_mode()
738 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; in mv88e6351_port_set_frame_mode()
741 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; in mv88e6351_port_set_frame_mode()
744 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; in mv88e6351_port_set_frame_mode()
747 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; in mv88e6351_port_set_frame_mode()
753 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6351_port_set_frame_mode()
760 u16 reg; in mv88e6185_port_set_forward_unknown() local
762 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6185_port_set_forward_unknown()
767 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; in mv88e6185_port_set_forward_unknown()
769 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; in mv88e6185_port_set_forward_unknown()
771 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6185_port_set_forward_unknown()
778 u16 reg; in mv88e6352_port_set_egress_floods() local
780 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); in mv88e6352_port_set_egress_floods()
784 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK; in mv88e6352_port_set_egress_floods()
787 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA; in mv88e6352_port_set_egress_floods()
789 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA; in mv88e6352_port_set_egress_floods()
791 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA; in mv88e6352_port_set_egress_floods()
793 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA; in mv88e6352_port_set_egress_floods()
795 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); in mv88e6352_port_set_egress_floods()
823 u16 reg; in mv88e6xxx_port_set_vlan_map() local
826 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_set_vlan_map()
830 reg &= ~mask; in mv88e6xxx_port_set_vlan_map()
831 reg |= map & mask; in mv88e6xxx_port_set_vlan_map()
833 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); in mv88e6xxx_port_set_vlan_map()
845 u16 reg; in mv88e6xxx_port_get_fid() local
849 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_get_fid()
853 *fid = (reg & 0xf000) >> 12; in mv88e6xxx_port_get_fid()
858 ®); in mv88e6xxx_port_get_fid()
862 *fid |= (reg & upper_mask) << 4; in mv88e6xxx_port_get_fid()
871 u16 reg; in mv88e6xxx_port_set_fid() local
878 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); in mv88e6xxx_port_set_fid()
882 reg &= 0x0fff; in mv88e6xxx_port_set_fid()
883 reg |= (fid & 0x000f) << 12; in mv88e6xxx_port_set_fid()
885 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); in mv88e6xxx_port_set_fid()
892 ®); in mv88e6xxx_port_set_fid()
896 reg &= ~upper_mask; in mv88e6xxx_port_set_fid()
897 reg |= (fid >> 4) & upper_mask; in mv88e6xxx_port_set_fid()
900 reg); in mv88e6xxx_port_set_fid()
914 u16 reg; in mv88e6xxx_port_get_pvid() local
918 ®); in mv88e6xxx_port_get_pvid()
922 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; in mv88e6xxx_port_get_pvid()
929 u16 reg; in mv88e6xxx_port_set_pvid() local
933 ®); in mv88e6xxx_port_set_pvid()
937 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; in mv88e6xxx_port_set_pvid()
938 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; in mv88e6xxx_port_set_pvid()
941 reg); in mv88e6xxx_port_set_pvid()
963 u16 reg; in mv88e6185_port_set_default_forward() local
965 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6185_port_set_default_forward()
970 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; in mv88e6185_port_set_default_forward()
972 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; in mv88e6185_port_set_default_forward()
974 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6185_port_set_default_forward()
993 u16 reg; in mv88e6095_port_set_upstream_port() local
995 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6095_port_set_upstream_port()
999 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; in mv88e6095_port_set_upstream_port()
1000 reg |= upstream_port; in mv88e6095_port_set_upstream_port()
1002 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6095_port_set_upstream_port()
1010 u16 reg; in mv88e6xxx_port_set_mirror() local
1014 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_mirror()
1031 reg &= ~bit; in mv88e6xxx_port_set_mirror()
1033 reg |= bit; in mv88e6xxx_port_set_mirror()
1035 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_mirror()
1045 u16 reg; in mv88e6xxx_port_set_8021q_mode() local
1048 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_8021q_mode()
1052 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; in mv88e6xxx_port_set_8021q_mode()
1053 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; in mv88e6xxx_port_set_8021q_mode()
1055 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_8021q_mode()
1067 u16 reg; in mv88e6xxx_port_set_map_da() local
1070 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6xxx_port_set_map_da()
1074 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; in mv88e6xxx_port_set_map_da()
1076 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6xxx_port_set_map_da()
1082 u16 reg; in mv88e6165_port_set_jumbo_size() local
1087 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); in mv88e6165_port_set_jumbo_size()
1091 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; in mv88e6165_port_set_jumbo_size()
1094 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; in mv88e6165_port_set_jumbo_size()
1096 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; in mv88e6165_port_set_jumbo_size()
1098 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; in mv88e6165_port_set_jumbo_size()
1102 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); in mv88e6165_port_set_jumbo_size()
1164 u16 reg; in mv88e6xxx_port_ieeepmt_write() local
1166 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | in mv88e6xxx_port_ieeepmt_write()
1171 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); in mv88e6xxx_port_ieeepmt_write()
1211 u16 reg, mask, val; in mv88e6352_port_set_policy() local
1269 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); in mv88e6352_port_set_policy()
1273 reg &= ~mask; in mv88e6352_port_set_policy()
1274 reg |= (val << shift) & mask; in mv88e6352_port_set_policy()
1276 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); in mv88e6352_port_set_policy()