Lines Matching defs:fman_qmi_regs

413 struct fman_qmi_regs {  struct
414 	u32 fmqm_gc;		/* General Configuration Register 0x00 */
415 	u32 res0004;		/* 0x04 */
416 	u32 fmqm_eie;		/* Error Interrupt Event Register 0x08 */
417 	u32 fmqm_eien;		/* Error Interrupt Enable Register 0x0c */
418 	u32 fmqm_eif;		/* Error Interrupt Force Register 0x10 */
419 	u32 fmqm_ie;		/* Interrupt Event Register 0x14 */
420 	u32 fmqm_ien;		/* Interrupt Enable Register 0x18 */
421 	u32 fmqm_if;		/* Interrupt Force Register 0x1c */
422 	u32 fmqm_gs;		/* Global Status Register 0x20 */
423 	u32 fmqm_ts;		/* Task Status Register 0x24 */
424 	u32 fmqm_etfc;		/* Enqueue Total Frame Counter 0x28 */
425 	u32 fmqm_dtfc;		/* Dequeue Total Frame Counter 0x2c */
426 	u32 fmqm_dc0;		/* Dequeue Counter 0 0x30 */
427 	u32 fmqm_dc1;		/* Dequeue Counter 1 0x34 */
428 	u32 fmqm_dc2;		/* Dequeue Counter 2 0x38 */
429 	u32 fmqm_dc3;		/* Dequeue Counter 3 0x3c */
430 	u32 fmqm_dfdc;		/* Dequeue FQID from Default Counter 0x40 */
431 	u32 fmqm_dfcc;		/* Dequeue FQID from Context Counter 0x44 */
432 	u32 fmqm_dffc;		/* Dequeue FQID from FD Counter 0x48 */
433 	u32 fmqm_dcc;		/* Dequeue Confirm Counter 0x4c */
434 	u32 res0050[7];		/* 0x50 - 0x6b */
435 	u32 fmqm_tapc;		/* Tnum Aging Period Control 0x6c */
436 	u32 fmqm_dmcvc;		/* Dequeue MAC Command Valid Counter 0x70 */
437 	u32 fmqm_difdcc;	/* Dequeue Invalid FD Command Counter 0x74 */
438 	u32 fmqm_da1v;		/* Dequeue A1 Valid Counter 0x78 */
439 	u32 res007c;		/* 0x7c */
440 	u32 fmqm_dtc;		/* 0x80 Debug Trap Counter 0x80 */
441 	u32 fmqm_efddd;		/* 0x84 Enqueue Frame desc Dynamic dbg 0x84 */
442 	u32 res0088[2];		/* 0x88 - 0x8f */
443 	struct {
452 	} dbg_traps[3];			/* 0x90 - 0xef */
453 	u8 res00f0[0x400 - 0xf0];	/* 0xf0 - 0x3ff */