977 	skb = __napi_alloc_skb(&rx_ring->q_vector->napi, ICE_RX_HDR_SIZE,  in ice_construct_skb()
1333 ice_update_itr(struct ice_q_vector *q_vector, struct ice_ring_container *rc)  in ice_update_itr()  argument
1348 	if (q_vector->itr_countdown) {  in ice_update_itr()
1353 	container_is_rx = (&q_vector->rx == rc);  in ice_update_itr()
1369 	prefetch(q_vector->vsi->port_info);  in ice_update_itr()
1381 		    (q_vector->tx.target_itr & ICE_ITR_ADAPTIVE_LATENCY)) {  in ice_update_itr()
1392 		    (q_vector->rx.target_itr & ICE_ITR_MASK) ==  in ice_update_itr()
1420 		itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);  in ice_update_itr()
1454 	itr = ice_adjust_itr_by_size_and_speed(q_vector->vsi->port_info,  in ice_update_itr()
1502 static void ice_update_ena_itr(struct ice_q_vector *q_vector)  in ice_update_ena_itr()  argument
1504 	struct ice_ring_container *tx = &q_vector->tx;  in ice_update_ena_itr()
1505 	struct ice_ring_container *rx = &q_vector->rx;  in ice_update_ena_itr()
1506 	struct ice_vsi *vsi = q_vector->vsi;  in ice_update_ena_itr()
1513 	if (q_vector->itr_countdown == ICE_IN_WB_ON_ITR_MODE) {  in ice_update_ena_itr()
1515 		wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx), itr_val);  in ice_update_ena_itr()
1522 		q_vector->itr_countdown = 0;  in ice_update_ena_itr()
1527 	ice_update_itr(q_vector, tx);  in ice_update_ena_itr()
1528 	ice_update_itr(q_vector, rx);  in ice_update_ena_itr()
1542 		q_vector->itr_countdown = ITR_COUNTDOWN_START;  in ice_update_ena_itr()
1551 		q_vector->itr_countdown = ITR_COUNTDOWN_START;  in ice_update_ena_itr()
1556 		q_vector->itr_countdown = ITR_COUNTDOWN_START;  in ice_update_ena_itr()
1560 		if (q_vector->itr_countdown)  in ice_update_ena_itr()
1561 			q_vector->itr_countdown--;  in ice_update_ena_itr()
1564 	if (!test_bit(__ICE_DOWN, q_vector->vsi->state))  in ice_update_ena_itr()
1565 		wr32(&q_vector->vsi->back->hw,  in ice_update_ena_itr()
1566 		     GLINT_DYN_CTL(q_vector->reg_idx),  in ice_update_ena_itr()
1584 static void ice_set_wb_on_itr(struct ice_q_vector *q_vector)  in ice_set_wb_on_itr()  argument
1586 	struct ice_vsi *vsi = q_vector->vsi;  in ice_set_wb_on_itr()
1589 	if (q_vector->itr_countdown == ICE_IN_WB_ON_ITR_MODE)  in ice_set_wb_on_itr()
1592 	if (q_vector->num_ring_rx)  in ice_set_wb_on_itr()
1593 		wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx),  in ice_set_wb_on_itr()
1597 	if (q_vector->num_ring_tx)  in ice_set_wb_on_itr()
1598 		wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx),  in ice_set_wb_on_itr()
1602 	q_vector->itr_countdown = ICE_IN_WB_ON_ITR_MODE;  in ice_set_wb_on_itr()
1616 	struct ice_q_vector *q_vector =  in ice_napi_poll()  local
1626 	ice_for_each_ring(ring, q_vector->tx) {  in ice_napi_poll()
1640 	if (unlikely(q_vector->num_ring_rx > 1))  in ice_napi_poll()
1645 		budget_per_ring = max_t(int, budget / q_vector->num_ring_rx, 1);  in ice_napi_poll()
1650 	ice_for_each_ring(ring, q_vector->rx) {  in ice_napi_poll()
1674 		ice_update_ena_itr(q_vector);  in ice_napi_poll()
1676 		ice_set_wb_on_itr(q_vector);  in ice_napi_poll()