Lines Matching refs:offset
211 static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) in u300_gpio_get() argument
215 return !!(readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset)); in u300_gpio_get()
218 static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in u300_gpio_set() argument
226 val = readl(U300_PIN_REG(offset, dor)); in u300_gpio_set()
228 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); in u300_gpio_set()
230 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); in u300_gpio_set()
235 static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in u300_gpio_direction_input() argument
242 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_direction_input()
244 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); in u300_gpio_direction_input()
245 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_direction_input()
250 static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in u300_gpio_direction_output() argument
259 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_direction_output()
265 ((offset & 0x07) << 1)); in u300_gpio_direction_output()
269 ((offset & 0x07) << 1)); in u300_gpio_direction_output()
271 << ((offset & 0x07) << 1)); in u300_gpio_direction_output()
272 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_direction_output()
274 u300_gpio_set(chip, offset, value); in u300_gpio_direction_output()
281 unsigned offset, in u300_gpio_config_get() argument
290 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset)); in u300_gpio_config_get()
293 drmode = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_config_get()
294 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); in u300_gpio_config_get()
295 drmode >>= ((offset & 0x07) << 1); in u300_gpio_config_get()
339 int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, in u300_gpio_config_set() argument
350 val = readl(U300_PIN_REG(offset, per)); in u300_gpio_config_set()
351 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); in u300_gpio_config_set()
354 val = readl(U300_PIN_REG(offset, per)); in u300_gpio_config_set()
355 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); in u300_gpio_config_set()
358 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
360 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
362 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
363 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
366 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
368 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
370 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
371 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
374 val = readl(U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
376 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
378 << ((offset & 0x07) << 1)); in u300_gpio_config_set()
379 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
401 static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) in u300_toggle_trigger() argument
405 val = readl(U300_PIN_REG(offset, icr)); in u300_toggle_trigger()
407 if (u300_gpio_get(&gpio->chip, offset)) { in u300_toggle_trigger()
409 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); in u300_toggle_trigger()
411 offset); in u300_toggle_trigger()
414 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); in u300_toggle_trigger()
416 offset); in u300_toggle_trigger()
425 int offset = d->hwirq; in u300_gpio_irq_type() local
437 offset); in u300_gpio_irq_type()
438 port->toggle_edge_mode |= U300_PIN_BIT(offset); in u300_gpio_irq_type()
439 u300_toggle_trigger(gpio, offset); in u300_gpio_irq_type()
442 offset); in u300_gpio_irq_type()
443 val = readl(U300_PIN_REG(offset, icr)); in u300_gpio_irq_type()
444 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); in u300_gpio_irq_type()
445 port->toggle_edge_mode &= ~U300_PIN_BIT(offset); in u300_gpio_irq_type()
448 offset); in u300_gpio_irq_type()
449 val = readl(U300_PIN_REG(offset, icr)); in u300_gpio_irq_type()
450 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); in u300_gpio_irq_type()
451 port->toggle_edge_mode &= ~U300_PIN_BIT(offset); in u300_gpio_irq_type()
462 int offset = d->hwirq; in u300_gpio_irq_enable() local
467 d->hwirq, port->name, offset); in u300_gpio_irq_enable()
469 val = readl(U300_PIN_REG(offset, ien)); in u300_gpio_irq_enable()
470 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); in u300_gpio_irq_enable()
478 int offset = d->hwirq; in u300_gpio_irq_disable() local
483 val = readl(U300_PIN_REG(offset, ien)); in u300_gpio_irq_disable()
484 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); in u300_gpio_irq_disable()
519 int offset = pinoffset + irqoffset; in u300_gpio_irq_handler() local
520 int pin_irq = irq_find_mapping(chip->irq.domain, offset); in u300_gpio_irq_handler()
523 pin_irq, offset); in u300_gpio_irq_handler()
529 if (port->toggle_edge_mode & U300_PIN_BIT(offset)) in u300_gpio_irq_handler()
530 u300_toggle_trigger(gpio, offset); in u300_gpio_irq_handler()
538 int offset, in u300_gpio_init_pin() argument
543 u300_gpio_direction_output(&gpio->chip, offset, conf->outval); in u300_gpio_init_pin()
546 u300_gpio_config_set(&gpio->chip, offset, in u300_gpio_init_pin()
550 u300_gpio_config_set(&gpio->chip, offset, in u300_gpio_init_pin()
554 offset, conf->outval); in u300_gpio_init_pin()
556 u300_gpio_direction_input(&gpio->chip, offset); in u300_gpio_init_pin()
559 u300_gpio_set(&gpio->chip, offset, 0); in u300_gpio_init_pin()
562 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode); in u300_gpio_init_pin()
565 offset, conf->bias_mode); in u300_gpio_init_pin()
577 int offset = (i*8) + j; in u300_gpio_init_coh901571() local
580 u300_gpio_init_pin(gpio, offset, conf); in u300_gpio_init_coh901571()
591 unsigned int offset; member
595 #define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
717 p->offset, p->pin_base, 1); in u300_gpio_probe()