Lines Matching refs:temp
60 u32 temp; in xhci_create_usb3_bos_desc() local
99 temp = readl(&xhci->cap_regs->hcc_params); in xhci_create_usb3_bos_desc()
100 if (HCC_LTC(temp)) in xhci_create_usb3_bos_desc()
105 temp = readl(&xhci->cap_regs->hcs_params3); in xhci_create_usb3_bos_desc()
106 buf[12] = HCS_U1_LATENCY(temp); in xhci_create_usb3_bos_desc()
107 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); in xhci_create_usb3_bos_desc()
172 u16 temp; in xhci_common_hub_descriptor() local
177 temp = 0; in xhci_common_hub_descriptor()
180 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
182 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
185 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
188 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
196 u16 temp; in xhci_usb2_hub_descriptor() local
206 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
207 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
580 u32 temp; in xhci_set_port_power() local
584 temp = readl(port->addr); in xhci_set_port_power()
587 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp); in xhci_set_port_power()
589 temp = xhci_port_state_to_neutral(temp); in xhci_set_port_power()
593 writel(temp | PORT_POWER, port->addr); in xhci_set_port_power()
597 writel(temp & ~PORT_POWER, port->addr); in xhci_set_port_power()
601 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_set_port_power()
603 if (temp) in xhci_set_port_power()
612 u32 temp; in xhci_port_set_test_mode() local
617 temp = readl(port->addr + PORTPMSC); in xhci_port_set_test_mode()
618 temp |= test_mode << PORT_TEST_MODE_SHIFT; in xhci_port_set_test_mode()
619 writel(temp, port->addr + PORTPMSC); in xhci_port_set_test_mode()
690 u32 temp; in xhci_set_link_state() local
694 temp = xhci_port_state_to_neutral(portsc); in xhci_set_link_state()
695 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
696 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
697 writel(temp, port->addr); in xhci_set_link_state()
701 portsc, temp); in xhci_set_link_state()
707 u32 temp; in xhci_set_remote_wake_mask() local
709 temp = readl(port->addr); in xhci_set_remote_wake_mask()
710 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
713 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
715 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
718 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
720 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
723 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
725 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
727 writel(temp, port->addr); in xhci_set_remote_wake_mask()
734 u32 temp; in xhci_test_and_clear_bit() local
736 temp = readl(port->addr); in xhci_test_and_clear_bit()
737 if (temp & port_bit) { in xhci_test_and_clear_bit()
738 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
739 temp |= port_bit; in xhci_test_and_clear_bit()
740 writel(temp, port->addr); in xhci_test_and_clear_bit()
1106 u32 temp, status; in xhci_hub_control() local
1157 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1158 if (temp == ~(u32)0) { in xhci_hub_control()
1163 trace_xhci_get_port_status(wIndex, temp); in xhci_hub_control()
1164 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1170 hcd->self.busnum, wIndex + 1, temp, status); in xhci_hub_control()
1183 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
1200 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1201 if (temp == ~(u32)0) { in xhci_hub_control()
1206 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1210 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1211 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
1223 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1224 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
1225 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1248 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1252 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1257 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1262 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1265 writel(temp | PORT_PE, ports[wIndex]->addr); in xhci_hub_control()
1266 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1276 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1300 if ((temp & PORT_CONNECT)) { in xhci_hub_control()
1310 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1314 if (!(temp & PORT_PE)) { in xhci_hub_control()
1334 u32 pls = temp & PORT_PLS_MASK; in xhci_hub_control()
1360 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1380 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1381 if ((temp & PORT_PLS_MASK) == XDEV_U3) in xhci_hub_control()
1385 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1399 temp = (temp | PORT_RESET); in xhci_hub_control()
1400 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1402 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1404 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1409 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1411 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1414 temp |= PORT_WR; in xhci_hub_control()
1415 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1416 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1421 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1422 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1423 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1424 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1429 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1430 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1431 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1432 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1448 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1454 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1455 if (temp == ~(u32)0) { in xhci_hub_control()
1461 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1464 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1466 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1467 if (temp & PORT_RESET) in xhci_hub_control()
1469 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1470 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1506 ports[wIndex]->addr, temp); in xhci_hub_control()
1510 ports[wIndex]->addr, temp); in xhci_hub_control()
1542 u32 temp, status; in xhci_hub_status_data() local
1573 temp = readl(ports[i]->addr); in xhci_hub_status_data()
1574 if (temp == ~(u32)0) { in xhci_hub_status_data()
1579 trace_xhci_hub_status_data(i, temp); in xhci_hub_status_data()
1581 if ((temp & mask) != 0 || in xhci_hub_status_data()
1588 if ((temp & PORT_RC)) in xhci_hub_status_data()
1590 if (temp & PORT_OC) in xhci_hub_status_data()
1773 u32 temp, portsc; in xhci_bus_resume() local
1792 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1793 temp &= ~CMD_EIE; in xhci_bus_resume()
1794 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1871 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1872 temp |= CMD_EIE; in xhci_bus_resume()
1873 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1874 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()