Lines Matching refs:reg1
137 .reg1 = WM8776_REG_DACLVOL,
147 .reg1 = WM8776_REG_DACCTRL1,
156 .reg1 = WM8776_REG_DACCTRL1,
163 .reg1 = WM8776_REG_HPLVOL,
174 .reg1 = WM8776_REG_PWRDOWN,
181 .reg1 = WM8776_REG_HPLVOL,
190 .reg1 = WM8776_REG_OUTMUX,
196 .reg1 = WM8776_REG_OUTMUX,
202 .reg1 = WM8776_REG_DACCTRL1,
208 .reg1 = WM8776_REG_PHASESWAP,
217 .reg1 = WM8776_REG_DACCTRL2,
224 .reg1 = WM8776_REG_ADCLVOL,
234 .reg1 = WM8776_REG_ADCMUX,
243 .reg1 = WM8776_REG_ADCMUX,
249 .reg1 = WM8776_REG_ADCMUX,
255 .reg1 = WM8776_REG_ADCMUX,
261 .reg1 = WM8776_REG_ADCMUX,
267 .reg1 = WM8776_REG_ADCMUX,
283 .reg1 = WM8776_REG_ALCCTRL1,
294 .reg1 = WM8776_REG_ALCCTRL3,
305 .reg1 = WM8776_REG_ALCCTRL3,
315 .reg1 = WM8776_REG_LIMITER,
323 .reg1 = WM8776_REG_LIMITER,
333 .reg1 = WM8776_REG_ALCCTRL1,
345 .reg1 = WM8776_REG_ALCCTRL3,
356 .reg1 = WM8776_REG_ALCCTRL3,
364 .reg1 = WM8776_REG_ALCCTRL1,
374 .reg1 = WM8776_REG_LIMITER,
388 .reg1 = WM8776_REG_ALCCTRL2,
395 .reg1 = WM8776_REG_NOISEGATE,
403 .reg1 = WM8776_REG_NOISEGATE,
489 val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1; in snd_wm8776_ctl_get()
527 val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; in snd_wm8776_ctl_put()
531 wm->ctl[n].reg1 == wm->ctl[n].reg2) { in snd_wm8776_ctl_put()
535 snd_wm8776_write(wm, wm->ctl[n].reg1, val); in snd_wm8776_ctl_put()
538 wm->ctl[n].reg1 != wm->ctl[n].reg2) { in snd_wm8776_ctl_put()