Lines Matching refs:bclk
1565 int lrclk, bclk, fmt_val; in wm2200_set_fmt() local
1568 bclk = 0; in wm2200_set_fmt()
1590 bclk |= WM2200_AIF1_BCLK_MSTR; in wm2200_set_fmt()
1594 bclk |= WM2200_AIF1_BCLK_MSTR; in wm2200_set_fmt()
1606 bclk |= WM2200_AIF1_BCLK_INV; in wm2200_set_fmt()
1610 bclk |= WM2200_AIF1_BCLK_INV; in wm2200_set_fmt()
1620 WM2200_AIF1_BCLK_INV, bclk); in wm2200_set_fmt()
1698 int i, bclk, lrclk, wl, fl, sr_code; in wm2200_hw_params() local
1713 bclk = snd_soc_params_to_bclk(params); in wm2200_hw_params()
1714 if (bclk < 0) in wm2200_hw_params()
1715 return bclk; in wm2200_hw_params()
1733 bclk, wm2200->sysclk); in wm2200_hw_params()
1741 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0)) in wm2200_hw_params()
1746 bclk, wm2200->sysclk); in wm2200_hw_params()
1750 bclk = i; in wm2200_hw_params()
1751 dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]); in wm2200_hw_params()
1753 WM2200_AIF1_BCLK_DIV_MASK, bclk); in wm2200_hw_params()
1755 lrclk = bclk_rates[bclk] / params_rate(params); in wm2200_hw_params()
1756 dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk); in wm2200_hw_params()