Lines Matching refs:val
81 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val) in hi6210_write_reg() argument
83 writel(val, i2s->base + reg); in hi6210_write_reg()
96 u32 val; in hi6210_i2s_startup() local
99 regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val); in hi6210_i2s_startup()
100 if (val & BIT(4)) in hi6210_i2s_startup()
127 val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK); in hi6210_i2s_startup()
128 val |= 0x3f; in hi6210_i2s_startup()
129 hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val); in hi6210_i2s_startup()
133 val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1); in hi6210_i2s_startup()
134 val |= (BIT(5) | BIT(4)); in hi6210_i2s_startup()
135 hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val); in hi6210_i2s_startup()
137 val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1); in hi6210_i2s_startup()
138 val &= ~(BIT(5) | BIT(4)); in hi6210_i2s_startup()
139 hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val); in hi6210_i2s_startup()
142 val = hi6210_read_reg(i2s, HII2S_SW_RST_N); in hi6210_i2s_startup()
143 val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK << in hi6210_i2s_startup()
145 val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT); in hi6210_i2s_startup()
146 hi6210_write_reg(i2s, HII2S_SW_RST_N, val); in hi6210_i2s_startup()
148 val = hi6210_read_reg(i2s, HII2S_MISC_CFG); in hi6210_i2s_startup()
150 val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL; in hi6210_i2s_startup()
152 val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL; in hi6210_i2s_startup()
153 val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL; in hi6210_i2s_startup()
155 val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL; in hi6210_i2s_startup()
157 val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL; in hi6210_i2s_startup()
158 hi6210_write_reg(i2s, HII2S_MISC_CFG, val); in hi6210_i2s_startup()
160 val = hi6210_read_reg(i2s, HII2S_SW_RST_N); in hi6210_i2s_startup()
161 val |= HII2S_SW_RST_N__SW_RST_N; in hi6210_i2s_startup()
162 hi6210_write_reg(i2s, HII2S_SW_RST_N, val); in hi6210_i2s_startup()
187 u32 val; in hi6210_i2s_txctrl() local
192 val = hi6210_read_reg(i2s, HII2S_I2S_CFG); in hi6210_i2s_txctrl()
193 val |= HII2S_I2S_CFG__S2_IF_TX_EN; in hi6210_i2s_txctrl()
194 hi6210_write_reg(i2s, HII2S_I2S_CFG, val); in hi6210_i2s_txctrl()
197 val = hi6210_read_reg(i2s, HII2S_I2S_CFG); in hi6210_i2s_txctrl()
198 val &= ~HII2S_I2S_CFG__S2_IF_TX_EN; in hi6210_i2s_txctrl()
199 hi6210_write_reg(i2s, HII2S_I2S_CFG, val); in hi6210_i2s_txctrl()
207 u32 val; in hi6210_i2s_rxctrl() local
211 val = hi6210_read_reg(i2s, HII2S_I2S_CFG); in hi6210_i2s_rxctrl()
212 val |= HII2S_I2S_CFG__S2_IF_RX_EN; in hi6210_i2s_rxctrl()
213 hi6210_write_reg(i2s, HII2S_I2S_CFG, val); in hi6210_i2s_rxctrl()
215 val = hi6210_read_reg(i2s, HII2S_I2S_CFG); in hi6210_i2s_rxctrl()
216 val &= ~HII2S_I2S_CFG__S2_IF_RX_EN; in hi6210_i2s_rxctrl()
217 hi6210_write_reg(i2s, HII2S_I2S_CFG, val); in hi6210_i2s_rxctrl()
260 u32 val; in hi6210_i2s_hw_params() local
327 val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG); in hi6210_i2s_hw_params()
328 val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK << in hi6210_i2s_hw_params()
336 val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) | in hi6210_i2s_hw_params()
340 hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val); in hi6210_i2s_hw_params()
343 val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG); in hi6210_i2s_hw_params()
344 val |= (BIT(19) | BIT(18) | BIT(17) | in hi6210_i2s_hw_params()
350 hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val); in hi6210_i2s_hw_params()
353 val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG); in hi6210_i2s_hw_params()
354 val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN | in hi6210_i2s_hw_params()
360 val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN | in hi6210_i2s_hw_params()
362 hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val); in hi6210_i2s_hw_params()
365 val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG); in hi6210_i2s_hw_params()
366 val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE | in hi6210_i2s_hw_params()
368 hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val); in hi6210_i2s_hw_params()
370 val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG); in hi6210_i2s_hw_params()
371 val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE | in hi6210_i2s_hw_params()
375 hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val); in hi6210_i2s_hw_params()
381 val = hi6210_read_reg(i2s, HII2S_I2S_CFG); in hi6210_i2s_hw_params()
382 val |= HII2S_I2S_CFG__S2_MST_SLV; in hi6210_i2s_hw_params()
383 hi6210_write_reg(i2s, HII2S_I2S_CFG, val); in hi6210_i2s_hw_params()
387 val = hi6210_read_reg(i2s, HII2S_I2S_CFG); in hi6210_i2s_hw_params()
388 val &= ~HII2S_I2S_CFG__S2_MST_SLV; in hi6210_i2s_hw_params()
389 hi6210_write_reg(i2s, HII2S_I2S_CFG, val); in hi6210_i2s_hw_params()
411 val = hi6210_read_reg(i2s, HII2S_I2S_CFG); in hi6210_i2s_hw_params()
412 val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK << in hi6210_i2s_hw_params()
414 val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT; in hi6210_i2s_hw_params()
415 hi6210_write_reg(i2s, HII2S_I2S_CFG, val); in hi6210_i2s_hw_params()
418 val = hi6210_read_reg(i2s, HII2S_CLK_SEL); in hi6210_i2s_hw_params()
419 val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */ in hi6210_i2s_hw_params()
421 hi6210_write_reg(i2s, HII2S_CLK_SEL, val); in hi6210_i2s_hw_params()
432 val = hi6210_read_reg(i2s, HII2S_I2S_CFG); in hi6210_i2s_hw_params()
433 val |= HII2S_I2S_CFG__S2_FRAME_MODE; in hi6210_i2s_hw_params()
434 hi6210_write_reg(i2s, HII2S_I2S_CFG, val); in hi6210_i2s_hw_params()
437 val = hi6210_read_reg(i2s, HII2S_I2S_CFG); in hi6210_i2s_hw_params()
438 val &= ~HII2S_I2S_CFG__S2_FRAME_MODE; in hi6210_i2s_hw_params()
439 hi6210_write_reg(i2s, HII2S_I2S_CFG, val); in hi6210_i2s_hw_params()
444 val = hi6210_read_reg(i2s, HII2S_I2S_CFG); in hi6210_i2s_hw_params()
445 val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT; in hi6210_i2s_hw_params()
446 val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK << in hi6210_i2s_hw_params()
448 val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK << in hi6210_i2s_hw_params()
450 val |= signed_data; in hi6210_i2s_hw_params()
451 val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT); in hi6210_i2s_hw_params()
452 hi6210_write_reg(i2s, HII2S_I2S_CFG, val); in hi6210_i2s_hw_params()
459 val = hi6210_read_reg(i2s, HII2S_FS_CFG); in hi6210_i2s_hw_params()
460 val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT); in hi6210_i2s_hw_params()
461 val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT); in hi6210_i2s_hw_params()
462 val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK << in hi6210_i2s_hw_params()
464 val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK << in hi6210_i2s_hw_params()
466 val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT); in hi6210_i2s_hw_params()
467 val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT); in hi6210_i2s_hw_params()
468 val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT); in hi6210_i2s_hw_params()
469 val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT); in hi6210_i2s_hw_params()
470 hi6210_write_reg(i2s, HII2S_FS_CFG, val); in hi6210_i2s_hw_params()