103 	unsigned long val;  in zx_i2s_tx_en()  local
105 	val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);  in zx_i2s_tx_en()
107 		val |= ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN;  in zx_i2s_tx_en()
109 		val &= ~(ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN);  in zx_i2s_tx_en()
110 	writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);  in zx_i2s_tx_en()
115 	unsigned long val;  in zx_i2s_rx_en()  local
117 	val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);  in zx_i2s_rx_en()
119 		val |= ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN;  in zx_i2s_rx_en()
121 		val &= ~(ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN);  in zx_i2s_rx_en()
122 	writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);  in zx_i2s_rx_en()
127 	unsigned long val;  in zx_i2s_tx_dma_en()  local
129 	val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);  in zx_i2s_tx_dma_en()
130 	val |= ZX_I2S_FIFO_CTRL_TX_RST | (I2S_DEAGULT_FIFO_THRES << 8);  in zx_i2s_tx_dma_en()
132 		val |= ZX_I2S_FIFO_CTRL_TX_DMA_EN;  in zx_i2s_tx_dma_en()
134 		val &= ~ZX_I2S_FIFO_CTRL_TX_DMA_EN;  in zx_i2s_tx_dma_en()
135 	writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);  in zx_i2s_tx_dma_en()
140 	unsigned long val;  in zx_i2s_rx_dma_en()  local
142 	val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);  in zx_i2s_rx_dma_en()
143 	val |= ZX_I2S_FIFO_CTRL_RX_RST | (I2S_DEAGULT_FIFO_THRES << 16);  in zx_i2s_rx_dma_en()
145 		val |= ZX_I2S_FIFO_CTRL_RX_DMA_EN;  in zx_i2s_rx_dma_en()
147 		val &= ~ZX_I2S_FIFO_CTRL_RX_DMA_EN;  in zx_i2s_rx_dma_en()
148 	writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);  in zx_i2s_rx_dma_en()
178 	unsigned long val;  in zx_i2s_set_fmt()  local
180 	val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);  in zx_i2s_set_fmt()
181 	val &= ~(ZX_I2S_TIMING_TIMING_MASK | ZX_I2S_TIMING_ALIGN_MASK |  in zx_i2s_set_fmt()
187 		val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_STD_I2S);  in zx_i2s_set_fmt()
190 		val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_MSB_JUSTIF);  in zx_i2s_set_fmt()
193 		val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_LSB_JUSTIF);  in zx_i2s_set_fmt()
204 		val |= ZX_I2S_TIMING_SLAVE;  in zx_i2s_set_fmt()
209 		val |= ZX_I2S_TIMING_MAST;  in zx_i2s_set_fmt()
216 	writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);  in zx_i2s_set_fmt()
228 	unsigned long val;  in zx_i2s_hw_params()  local
234 	val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);  in zx_i2s_hw_params()
235 	val &= ~(ZX_I2S_TIMING_TS_WIDTH_MASK | ZX_I2S_TIMING_DATA_SIZE_MASK |  in zx_i2s_hw_params()
253 	val |= ZX_I2S_TIMING_TS_WIDTH(ts_width) | ZX_I2S_TIMING_DATA_SIZE(len);  in zx_i2s_hw_params()
272 	val |= ZX_I2S_TIMING_LANE(lane);  in zx_i2s_hw_params()
273 	val |= ZX_I2S_TIMING_TSCFG(chn_cfg);  in zx_i2s_hw_params()
274 	val |= ZX_I2S_TIMING_CHN(ch_num);  in zx_i2s_hw_params()
275 	writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);  in zx_i2s_hw_params()