1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25 /*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28 #ifndef __AST_DRV_H__
29 #define __AST_DRV_H__
30
31 #include <linux/types.h>
32 #include <linux/io.h>
33 #include <linux/i2c.h>
34 #include <linux/i2c-algo-bit.h>
35
36 #include <drm/drm_connector.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_mode.h>
40 #include <drm/drm_framebuffer.h>
41 #include <drm/drm_fb_helper.h>
42
43 #define DRIVER_AUTHOR "Dave Airlie"
44
45 #define DRIVER_NAME "ast"
46 #define DRIVER_DESC "AST"
47 #define DRIVER_DATE "20120228"
48
49 #define DRIVER_MAJOR 0
50 #define DRIVER_MINOR 1
51 #define DRIVER_PATCHLEVEL 0
52
53 #define PCI_CHIP_AST2000 0x2000
54 #define PCI_CHIP_AST2100 0x2010
55
56
57 enum ast_chip {
58 AST2000,
59 AST2100,
60 AST1100,
61 AST2200,
62 AST2150,
63 AST2300,
64 AST2400,
65 AST2500,
66 };
67
68 enum ast_tx_chip {
69 AST_TX_NONE,
70 AST_TX_SIL164,
71 AST_TX_ITE66121,
72 AST_TX_DP501,
73 };
74
75 #define AST_DRAM_512Mx16 0
76 #define AST_DRAM_1Gx16 1
77 #define AST_DRAM_512Mx32 2
78 #define AST_DRAM_1Gx32 3
79 #define AST_DRAM_2Gx16 6
80 #define AST_DRAM_4Gx16 7
81 #define AST_DRAM_8Gx16 8
82
83
84 #define AST_MAX_HWC_WIDTH 64
85 #define AST_MAX_HWC_HEIGHT 64
86
87 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
88 #define AST_HWC_SIGNATURE_SIZE 32
89
90 #define AST_DEFAULT_HWC_NUM 2
91
92 /* define for signature structure */
93 #define AST_HWC_SIGNATURE_CHECKSUM 0x00
94 #define AST_HWC_SIGNATURE_SizeX 0x04
95 #define AST_HWC_SIGNATURE_SizeY 0x08
96 #define AST_HWC_SIGNATURE_X 0x0C
97 #define AST_HWC_SIGNATURE_Y 0x10
98 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14
99 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18
100
101 struct ast_i2c_chan {
102 struct i2c_adapter adapter;
103 struct drm_device *dev;
104 struct i2c_algo_bit_data bit;
105 };
106
107 struct ast_connector {
108 struct drm_connector base;
109 struct ast_i2c_chan *i2c;
110 };
111
112 static inline struct ast_connector *
to_ast_connector(struct drm_connector * connector)113 to_ast_connector(struct drm_connector *connector)
114 {
115 return container_of(connector, struct ast_connector, base);
116 }
117
118 struct ast_private {
119 struct drm_device base;
120
121 void __iomem *regs;
122 void __iomem *ioregs;
123 void __iomem *dp501_fw_buf;
124
125 enum ast_chip chip;
126 bool vga2_clone;
127 uint32_t dram_bus_width;
128 uint32_t dram_type;
129 uint32_t mclk;
130
131 int fb_mtrr;
132
133 struct {
134 struct drm_gem_vram_object *gbo[AST_DEFAULT_HWC_NUM];
135 void __iomem *vaddr[AST_DEFAULT_HWC_NUM];
136 unsigned int next_index;
137 } cursor;
138
139 struct drm_plane primary_plane;
140 struct drm_plane cursor_plane;
141 struct drm_crtc crtc;
142 struct drm_encoder encoder;
143 struct ast_connector connector;
144
145 bool support_wide_screen;
146 enum {
147 ast_use_p2a,
148 ast_use_dt,
149 ast_use_defaults
150 } config_mode;
151
152 enum ast_tx_chip tx_chip_type;
153 u8 dp501_maxclk;
154 u8 *dp501_fw_addr;
155 const struct firmware *dp501_fw; /* dp501 fw */
156 };
157
to_ast_private(struct drm_device * dev)158 static inline struct ast_private *to_ast_private(struct drm_device *dev)
159 {
160 return container_of(dev, struct ast_private, base);
161 }
162
163 struct ast_private *ast_device_create(struct drm_driver *drv,
164 struct pci_dev *pdev,
165 unsigned long flags);
166
167 #define AST_IO_AR_PORT_WRITE (0x40)
168 #define AST_IO_MISC_PORT_WRITE (0x42)
169 #define AST_IO_VGA_ENABLE_PORT (0x43)
170 #define AST_IO_SEQ_PORT (0x44)
171 #define AST_IO_DAC_INDEX_READ (0x47)
172 #define AST_IO_DAC_INDEX_WRITE (0x48)
173 #define AST_IO_DAC_DATA (0x49)
174 #define AST_IO_GR_PORT (0x4E)
175 #define AST_IO_CRTC_PORT (0x54)
176 #define AST_IO_INPUT_STATUS1_READ (0x5A)
177 #define AST_IO_MISC_PORT_READ (0x4C)
178
179 #define AST_IO_MM_OFFSET (0x380)
180
181 #define AST_IO_VGAIR1_VREFRESH BIT(3)
182
183 #define __ast_read(x) \
184 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
185 u##x val = 0;\
186 val = ioread##x(ast->regs + reg); \
187 return val;\
188 }
189
190 __ast_read(8);
191 __ast_read(16);
192 __ast_read(32)
193
194 #define __ast_io_read(x) \
195 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
196 u##x val = 0;\
197 val = ioread##x(ast->ioregs + reg); \
198 return val;\
199 }
200
201 __ast_io_read(8);
202 __ast_io_read(16);
203 __ast_io_read(32);
204
205 #define __ast_write(x) \
206 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
207 iowrite##x(val, ast->regs + reg);\
208 }
209
210 __ast_write(8);
211 __ast_write(16);
212 __ast_write(32);
213
214 #define __ast_io_write(x) \
215 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
216 iowrite##x(val, ast->ioregs + reg);\
217 }
218
219 __ast_io_write(8);
220 __ast_io_write(16);
221 #undef __ast_io_write
222
ast_set_index_reg(struct ast_private * ast,uint32_t base,uint8_t index,uint8_t val)223 static inline void ast_set_index_reg(struct ast_private *ast,
224 uint32_t base, uint8_t index,
225 uint8_t val)
226 {
227 ast_io_write16(ast, base, ((u16)val << 8) | index);
228 }
229
230 void ast_set_index_reg_mask(struct ast_private *ast,
231 uint32_t base, uint8_t index,
232 uint8_t mask, uint8_t val);
233 uint8_t ast_get_index_reg(struct ast_private *ast,
234 uint32_t base, uint8_t index);
235 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
236 uint32_t base, uint8_t index, uint8_t mask);
237
ast_open_key(struct ast_private * ast)238 static inline void ast_open_key(struct ast_private *ast)
239 {
240 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
241 }
242
243 #define AST_VIDMEM_SIZE_8M 0x00800000
244 #define AST_VIDMEM_SIZE_16M 0x01000000
245 #define AST_VIDMEM_SIZE_32M 0x02000000
246 #define AST_VIDMEM_SIZE_64M 0x04000000
247 #define AST_VIDMEM_SIZE_128M 0x08000000
248
249 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
250
251 struct ast_vbios_stdtable {
252 u8 misc;
253 u8 seq[4];
254 u8 crtc[25];
255 u8 ar[20];
256 u8 gr[9];
257 };
258
259 struct ast_vbios_enhtable {
260 u32 ht;
261 u32 hde;
262 u32 hfp;
263 u32 hsync;
264 u32 vt;
265 u32 vde;
266 u32 vfp;
267 u32 vsync;
268 u32 dclk_index;
269 u32 flags;
270 u32 refresh_rate;
271 u32 refresh_rate_index;
272 u32 mode_id;
273 };
274
275 struct ast_vbios_dclk_info {
276 u8 param1;
277 u8 param2;
278 u8 param3;
279 };
280
281 struct ast_vbios_mode_info {
282 const struct ast_vbios_stdtable *std_table;
283 const struct ast_vbios_enhtable *enh_table;
284 };
285
286 struct ast_crtc_state {
287 struct drm_crtc_state base;
288
289 /* Last known format of primary plane */
290 const struct drm_format_info *format;
291
292 struct ast_vbios_mode_info vbios_mode_info;
293 };
294
295 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
296
297 int ast_mode_config_init(struct ast_private *ast);
298
299 #define AST_MM_ALIGN_SHIFT 4
300 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
301
302 #define AST_DP501_FW_VERSION_MASK GENMASK(7, 4)
303 #define AST_DP501_FW_VERSION_1 BIT(4)
304 #define AST_DP501_PNP_CONNECTED BIT(1)
305
306 #define AST_DP501_DEFAULT_DCLK 65
307
308 #define AST_DP501_GBL_VERSION 0xf000
309 #define AST_DP501_PNPMONITOR 0xf010
310 #define AST_DP501_LINKRATE 0xf014
311 #define AST_DP501_EDID_DATA 0xf020
312
313 int ast_mm_init(struct ast_private *ast);
314
315 /* ast post */
316 void ast_enable_vga(struct drm_device *dev);
317 void ast_enable_mmio(struct drm_device *dev);
318 bool ast_is_vga_enabled(struct drm_device *dev);
319 void ast_post_gpu(struct drm_device *dev);
320 u32 ast_mindwm(struct ast_private *ast, u32 r);
321 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
322 /* ast dp501 */
323 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
324 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
325 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
326 u8 ast_get_dp501_max_clk(struct drm_device *dev);
327 void ast_init_3rdtx(struct drm_device *dev);
328
329 /* ast_cursor.c */
330 int ast_cursor_init(struct ast_private *ast);
331 int ast_cursor_blit(struct ast_private *ast, struct drm_framebuffer *fb);
332 void ast_cursor_page_flip(struct ast_private *ast);
333 void ast_cursor_show(struct ast_private *ast, int x, int y,
334 unsigned int offset_x, unsigned int offset_y);
335 void ast_cursor_hide(struct ast_private *ast);
336
337 #endif
338