1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/include/asm/kvm_host.h:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
13
14 #include <linux/arm-smccc.h>
15 #include <linux/bitmap.h>
16 #include <linux/types.h>
17 #include <linux/jump_label.h>
18 #include <linux/kvm_types.h>
19 #include <linux/percpu.h>
20 #include <linux/psci.h>
21 #include <asm/arch_gicv3.h>
22 #include <asm/barrier.h>
23 #include <asm/cpufeature.h>
24 #include <asm/cputype.h>
25 #include <asm/daifflags.h>
26 #include <asm/fpsimd.h>
27 #include <asm/kvm.h>
28 #include <asm/kvm_asm.h>
29 #include <asm/thread_info.h>
30
31 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
32
33 #define KVM_USER_MEM_SLOTS 512
34 #define KVM_HALT_POLL_NS_DEFAULT 500000
35
36 #include <kvm/arm_vgic.h>
37 #include <kvm/arm_arch_timer.h>
38 #include <kvm/arm_pmu.h>
39
40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
41
42 #define KVM_VCPU_MAX_FEATURES 7
43
44 #define KVM_REQ_SLEEP \
45 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
46 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
47 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
48 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3)
49 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4)
50
51 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
52 KVM_DIRTY_LOG_INITIALLY_SET)
53
54 /*
55 * Mode of operation configurable with kvm-arm.mode early param.
56 * See Documentation/admin-guide/kernel-parameters.txt for more information.
57 */
58 enum kvm_mode {
59 KVM_MODE_DEFAULT,
60 KVM_MODE_PROTECTED,
61 KVM_MODE_NONE,
62 };
63 enum kvm_mode kvm_get_mode(void);
64
65 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
66
67 extern unsigned int kvm_sve_max_vl;
68 int kvm_arm_init_sve(void);
69
70 int __attribute_const__ kvm_target_cpu(void);
71 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
72 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
73
74 struct kvm_vmid {
75 /* The VMID generation used for the virt. memory system */
76 u64 vmid_gen;
77 u32 vmid;
78 };
79
80 struct kvm_s2_mmu {
81 struct kvm_vmid vmid;
82
83 /*
84 * stage2 entry level table
85 *
86 * Two kvm_s2_mmu structures in the same VM can point to the same
87 * pgd here. This happens when running a guest using a
88 * translation regime that isn't affected by its own stage-2
89 * translation, such as a non-VHE hypervisor running at vEL2, or
90 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the
91 * canonical stage-2 page tables.
92 */
93 phys_addr_t pgd_phys;
94 struct kvm_pgtable *pgt;
95
96 /* The last vcpu id that ran on each physical CPU */
97 int __percpu *last_vcpu_ran;
98
99 struct kvm_arch *arch;
100 };
101
102 struct kvm_arch_memory_slot {
103 };
104
105 struct kvm_arch {
106 struct kvm_s2_mmu mmu;
107
108 /* VTCR_EL2 value for this VM */
109 u64 vtcr;
110
111 /* The maximum number of vCPUs depends on the used GIC model */
112 int max_vcpus;
113
114 /* Interrupt controller */
115 struct vgic_dist vgic;
116
117 /* Mandated version of PSCI */
118 u32 psci_version;
119
120 /*
121 * If we encounter a data abort without valid instruction syndrome
122 * information, report this to user space. User space can (and
123 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
124 * supported.
125 */
126 bool return_nisv_io_abort_to_user;
127
128 /*
129 * VM-wide PMU filter, implemented as a bitmap and big enough for
130 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
131 */
132 unsigned long *pmu_filter;
133 unsigned int pmuver;
134
135 u8 pfr0_csv2;
136 u8 pfr0_csv3;
137 };
138
139 struct kvm_vcpu_fault_info {
140 u32 esr_el2; /* Hyp Syndrom Register */
141 u64 far_el2; /* Hyp Fault Address Register */
142 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
143 u64 disr_el1; /* Deferred [SError] Status Register */
144 };
145
146 enum vcpu_sysreg {
147 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */
148 MPIDR_EL1, /* MultiProcessor Affinity Register */
149 CSSELR_EL1, /* Cache Size Selection Register */
150 SCTLR_EL1, /* System Control Register */
151 ACTLR_EL1, /* Auxiliary Control Register */
152 CPACR_EL1, /* Coprocessor Access Control */
153 ZCR_EL1, /* SVE Control */
154 TTBR0_EL1, /* Translation Table Base Register 0 */
155 TTBR1_EL1, /* Translation Table Base Register 1 */
156 TCR_EL1, /* Translation Control Register */
157 ESR_EL1, /* Exception Syndrome Register */
158 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
159 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
160 FAR_EL1, /* Fault Address Register */
161 MAIR_EL1, /* Memory Attribute Indirection Register */
162 VBAR_EL1, /* Vector Base Address Register */
163 CONTEXTIDR_EL1, /* Context ID Register */
164 TPIDR_EL0, /* Thread ID, User R/W */
165 TPIDRRO_EL0, /* Thread ID, User R/O */
166 TPIDR_EL1, /* Thread ID, Privileged */
167 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
168 CNTKCTL_EL1, /* Timer Control Register (EL1) */
169 PAR_EL1, /* Physical Address Register */
170 MDSCR_EL1, /* Monitor Debug System Control Register */
171 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
172 DISR_EL1, /* Deferred Interrupt Status Register */
173
174 /* Performance Monitors Registers */
175 PMCR_EL0, /* Control Register */
176 PMSELR_EL0, /* Event Counter Selection Register */
177 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
178 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
179 PMCCNTR_EL0, /* Cycle Counter Register */
180 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
181 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
182 PMCCFILTR_EL0, /* Cycle Count Filter Register */
183 PMCNTENSET_EL0, /* Count Enable Set Register */
184 PMINTENSET_EL1, /* Interrupt Enable Set Register */
185 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
186 PMSWINC_EL0, /* Software Increment Register */
187 PMUSERENR_EL0, /* User Enable Register */
188
189 /* Pointer Authentication Registers in a strict increasing order. */
190 APIAKEYLO_EL1,
191 APIAKEYHI_EL1,
192 APIBKEYLO_EL1,
193 APIBKEYHI_EL1,
194 APDAKEYLO_EL1,
195 APDAKEYHI_EL1,
196 APDBKEYLO_EL1,
197 APDBKEYHI_EL1,
198 APGAKEYLO_EL1,
199 APGAKEYHI_EL1,
200
201 ELR_EL1,
202 SP_EL1,
203 SPSR_EL1,
204
205 CNTVOFF_EL2,
206 CNTV_CVAL_EL0,
207 CNTV_CTL_EL0,
208 CNTP_CVAL_EL0,
209 CNTP_CTL_EL0,
210
211 /* 32bit specific registers. Keep them at the end of the range */
212 DACR32_EL2, /* Domain Access Control Register */
213 IFSR32_EL2, /* Instruction Fault Status Register */
214 FPEXC32_EL2, /* Floating-Point Exception Control Register */
215 DBGVCR32_EL2, /* Debug Vector Catch Register */
216
217 NR_SYS_REGS /* Nothing after this line! */
218 };
219
220 struct kvm_cpu_context {
221 struct user_pt_regs regs; /* sp = sp_el0 */
222
223 u64 spsr_abt;
224 u64 spsr_und;
225 u64 spsr_irq;
226 u64 spsr_fiq;
227
228 struct user_fpsimd_state fp_regs;
229
230 u64 sys_regs[NR_SYS_REGS];
231
232 struct kvm_vcpu *__hyp_running_vcpu;
233 };
234
235 struct kvm_pmu_events {
236 u32 events_host;
237 u32 events_guest;
238 };
239
240 struct kvm_host_data {
241 struct kvm_cpu_context host_ctxt;
242 struct kvm_pmu_events pmu_events;
243 };
244
245 struct kvm_host_psci_config {
246 /* PSCI version used by host. */
247 u32 version;
248
249 /* Function IDs used by host if version is v0.1. */
250 struct psci_0_1_function_ids function_ids_0_1;
251
252 bool psci_0_1_cpu_suspend_implemented;
253 bool psci_0_1_cpu_on_implemented;
254 bool psci_0_1_cpu_off_implemented;
255 bool psci_0_1_migrate_implemented;
256 };
257
258 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
259 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
260
261 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
262 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
263
264 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
265 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
266
267 struct vcpu_reset_state {
268 unsigned long pc;
269 unsigned long r0;
270 bool be;
271 bool reset;
272 };
273
274 struct kvm_vcpu_arch {
275 struct kvm_cpu_context ctxt;
276 void *sve_state;
277 unsigned int sve_max_vl;
278
279 /* Stage 2 paging state used by the hardware on next switch */
280 struct kvm_s2_mmu *hw_mmu;
281
282 /* HYP configuration */
283 u64 hcr_el2;
284 u32 mdcr_el2;
285
286 /* Exception Information */
287 struct kvm_vcpu_fault_info fault;
288
289 /* State of various workarounds, see kvm_asm.h for bit assignment */
290 u64 workaround_flags;
291
292 /* Miscellaneous vcpu state flags */
293 u64 flags;
294
295 /*
296 * We maintain more than a single set of debug registers to support
297 * debugging the guest from the host and to maintain separate host and
298 * guest state during world switches. vcpu_debug_state are the debug
299 * registers of the vcpu as the guest sees them. host_debug_state are
300 * the host registers which are saved and restored during
301 * world switches. external_debug_state contains the debug
302 * values we want to debug the guest. This is set via the
303 * KVM_SET_GUEST_DEBUG ioctl.
304 *
305 * debug_ptr points to the set of debug registers that should be loaded
306 * onto the hardware when running the guest.
307 */
308 struct kvm_guest_debug_arch *debug_ptr;
309 struct kvm_guest_debug_arch vcpu_debug_state;
310 struct kvm_guest_debug_arch external_debug_state;
311
312 struct thread_info *host_thread_info; /* hyp VA */
313 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */
314
315 struct {
316 /* {Break,watch}point registers */
317 struct kvm_guest_debug_arch regs;
318 /* Statistical profiling extension */
319 u64 pmscr_el1;
320 /* Self-hosted trace */
321 u64 trfcr_el1;
322 } host_debug_state;
323
324 /* VGIC state */
325 struct vgic_cpu vgic_cpu;
326 struct arch_timer_cpu timer_cpu;
327 struct kvm_pmu pmu;
328
329 /*
330 * Anything that is not used directly from assembly code goes
331 * here.
332 */
333
334 /*
335 * Guest registers we preserve during guest debugging.
336 *
337 * These shadow registers are updated by the kvm_handle_sys_reg
338 * trap handler if the guest accesses or updates them while we
339 * are using guest debug.
340 */
341 struct {
342 u32 mdscr_el1;
343 } guest_debug_preserved;
344
345 /* vcpu power-off state */
346 bool power_off;
347
348 /* Don't run the guest (internal implementation need) */
349 bool pause;
350
351 /* Cache some mmu pages needed inside spinlock regions */
352 struct kvm_mmu_memory_cache mmu_page_cache;
353
354 /* Target CPU and feature flags */
355 int target;
356 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
357
358 /* Detect first run of a vcpu */
359 bool has_run_once;
360
361 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
362 u64 vsesr_el2;
363
364 /* Additional reset state */
365 struct vcpu_reset_state reset_state;
366
367 /* True when deferrable sysregs are loaded on the physical CPU,
368 * see kvm_vcpu_load_sysregs_vhe and kvm_vcpu_put_sysregs_vhe. */
369 bool sysregs_loaded_on_cpu;
370
371 /* Guest PV state */
372 struct {
373 u64 last_steal;
374 gpa_t base;
375 } steal;
376 };
377
378 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
379 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \
380 sve_ffr_offset((vcpu)->arch.sve_max_vl))
381
382 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl)
383
384 #define vcpu_sve_state_size(vcpu) ({ \
385 size_t __size_ret; \
386 unsigned int __vcpu_vq; \
387 \
388 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \
389 __size_ret = 0; \
390 } else { \
391 __vcpu_vq = vcpu_sve_max_vq(vcpu); \
392 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \
393 } \
394 \
395 __size_ret; \
396 })
397
398 /* vcpu_arch flags field values: */
399 #define KVM_ARM64_DEBUG_DIRTY (1 << 0)
400 #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */
401 #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */
402 #define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */
403 #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */
404 #define KVM_ARM64_GUEST_HAS_SVE (1 << 5) /* SVE exposed to guest */
405 #define KVM_ARM64_VCPU_SVE_FINALIZED (1 << 6) /* SVE config completed */
406 #define KVM_ARM64_GUEST_HAS_PTRAUTH (1 << 7) /* PTRAUTH exposed to guest */
407 #define KVM_ARM64_PENDING_EXCEPTION (1 << 8) /* Exception pending */
408 #define KVM_ARM64_EXCEPT_MASK (7 << 9) /* Target EL/MODE */
409 #define KVM_ARM64_DEBUG_STATE_SAVE_SPE (1 << 12) /* Save SPE context if active */
410 #define KVM_ARM64_DEBUG_STATE_SAVE_TRBE (1 << 13) /* Save TRBE context if active */
411
412 /*
413 * When KVM_ARM64_PENDING_EXCEPTION is set, KVM_ARM64_EXCEPT_MASK can
414 * take the following values:
415 *
416 * For AArch32 EL1:
417 */
418 #define KVM_ARM64_EXCEPT_AA32_UND (0 << 9)
419 #define KVM_ARM64_EXCEPT_AA32_IABT (1 << 9)
420 #define KVM_ARM64_EXCEPT_AA32_DABT (2 << 9)
421 /* For AArch64: */
422 #define KVM_ARM64_EXCEPT_AA64_ELx_SYNC (0 << 9)
423 #define KVM_ARM64_EXCEPT_AA64_ELx_IRQ (1 << 9)
424 #define KVM_ARM64_EXCEPT_AA64_ELx_FIQ (2 << 9)
425 #define KVM_ARM64_EXCEPT_AA64_ELx_SERR (3 << 9)
426 #define KVM_ARM64_EXCEPT_AA64_EL1 (0 << 11)
427 #define KVM_ARM64_EXCEPT_AA64_EL2 (1 << 11)
428
429 /*
430 * Overlaps with KVM_ARM64_EXCEPT_MASK on purpose so that it can't be
431 * set together with an exception...
432 */
433 #define KVM_ARM64_INCREMENT_PC (1 << 9) /* Increment PC */
434
435 #define vcpu_has_sve(vcpu) (system_supports_sve() && \
436 ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE))
437
438 #ifdef CONFIG_ARM64_PTR_AUTH
439 #define vcpu_has_ptrauth(vcpu) \
440 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \
441 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \
442 (vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH)
443 #else
444 #define vcpu_has_ptrauth(vcpu) false
445 #endif
446
447 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs)
448
449 /*
450 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
451 * memory backed version of a register, and not the one most recently
452 * accessed by a running VCPU. For example, for userspace access or
453 * for system registers that are never context switched, but only
454 * emulated.
455 */
456 #define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)])
457
458 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
459
460 #define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r)))
461
462 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
463 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
464
__vcpu_read_sys_reg_from_cpu(int reg,u64 * val)465 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
466 {
467 /*
468 * *** VHE ONLY ***
469 *
470 * System registers listed in the switch are not saved on every
471 * exit from the guest but are only saved on vcpu_put.
472 *
473 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
474 * should never be listed below, because the guest cannot modify its
475 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
476 * thread when emulating cross-VCPU communication.
477 */
478 if (!has_vhe())
479 return false;
480
481 switch (reg) {
482 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break;
483 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
484 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
485 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
486 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
487 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
488 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
489 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
490 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
491 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
492 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
493 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
494 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
495 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
496 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
497 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
498 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
499 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
500 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
501 case PAR_EL1: *val = read_sysreg_par(); break;
502 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
503 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
504 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
505 default: return false;
506 }
507
508 return true;
509 }
510
__vcpu_write_sys_reg_to_cpu(u64 val,int reg)511 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
512 {
513 /*
514 * *** VHE ONLY ***
515 *
516 * System registers listed in the switch are not restored on every
517 * entry to the guest but are only restored on vcpu_load.
518 *
519 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
520 * should never be listed below, because the MPIDR should only be set
521 * once, before running the VCPU, and never changed later.
522 */
523 if (!has_vhe())
524 return false;
525
526 switch (reg) {
527 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break;
528 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
529 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
530 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
531 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
532 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
533 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
534 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
535 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
536 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
537 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
538 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
539 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
540 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
541 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
542 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
543 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
544 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
545 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
546 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
547 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
548 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
549 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
550 default: return false;
551 }
552
553 return true;
554 }
555
556 struct kvm_vm_stat {
557 ulong remote_tlb_flush;
558 };
559
560 struct kvm_vcpu_stat {
561 u64 halt_successful_poll;
562 u64 halt_attempted_poll;
563 u64 halt_poll_success_ns;
564 u64 halt_poll_fail_ns;
565 u64 halt_poll_invalid;
566 u64 halt_wakeup;
567 u64 hvc_exit_stat;
568 u64 wfe_exit_stat;
569 u64 wfi_exit_stat;
570 u64 mmio_exit_user;
571 u64 mmio_exit_kernel;
572 u64 exits;
573 };
574
575 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
576 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
577 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
578 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
579 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
580
581 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
582 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
583 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
584 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
585
586 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
587 struct kvm_vcpu_events *events);
588
589 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
590 struct kvm_vcpu_events *events);
591
592 #define KVM_ARCH_WANT_MMU_NOTIFIER
593 int kvm_unmap_hva_range(struct kvm *kvm,
594 unsigned long start, unsigned long end, unsigned flags);
595 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
596 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
597 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
598
599 void kvm_arm_halt_guest(struct kvm *kvm);
600 void kvm_arm_resume_guest(struct kvm *kvm);
601
602 #ifndef __KVM_NVHE_HYPERVISOR__
603 #define kvm_call_hyp_nvhe(f, ...) \
604 ({ \
605 struct arm_smccc_res res; \
606 \
607 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
608 ##__VA_ARGS__, &res); \
609 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \
610 \
611 res.a1; \
612 })
613
614 /*
615 * The couple of isb() below are there to guarantee the same behaviour
616 * on VHE as on !VHE, where the eret to EL1 acts as a context
617 * synchronization event.
618 */
619 #define kvm_call_hyp(f, ...) \
620 do { \
621 if (has_vhe()) { \
622 f(__VA_ARGS__); \
623 isb(); \
624 } else { \
625 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
626 } \
627 } while(0)
628
629 #define kvm_call_hyp_ret(f, ...) \
630 ({ \
631 typeof(f(__VA_ARGS__)) ret; \
632 \
633 if (has_vhe()) { \
634 ret = f(__VA_ARGS__); \
635 isb(); \
636 } else { \
637 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
638 } \
639 \
640 ret; \
641 })
642 #else /* __KVM_NVHE_HYPERVISOR__ */
643 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
644 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
645 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
646 #endif /* __KVM_NVHE_HYPERVISOR__ */
647
648 void force_vm_exit(const cpumask_t *mask);
649 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
650
651 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
652 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
653
654 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
655 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
656 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
657 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
658 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
659 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
660
661 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
662
663 void kvm_sys_reg_table_init(void);
664
665 /* MMIO helpers */
666 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
667 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
668
669 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
670 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
671
672 int kvm_perf_init(void);
673 int kvm_perf_teardown(void);
674
675 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
676 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
677 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
678
679 bool kvm_arm_pvtime_supported(void);
680 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
681 struct kvm_device_attr *attr);
682 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
683 struct kvm_device_attr *attr);
684 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
685 struct kvm_device_attr *attr);
686
kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch * vcpu_arch)687 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
688 {
689 vcpu_arch->steal.base = GPA_INVALID;
690 }
691
kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch * vcpu_arch)692 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
693 {
694 return (vcpu_arch->steal.base != GPA_INVALID);
695 }
696
697 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
698
699 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
700
701 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
702
kvm_init_host_cpu_context(struct kvm_cpu_context * cpu_ctxt)703 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
704 {
705 /* The host's MPIDR is immutable, so let's set it up at boot time */
706 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
707 }
708
kvm_system_needs_idmapped_vectors(void)709 static inline bool kvm_system_needs_idmapped_vectors(void)
710 {
711 return cpus_have_const_cap(ARM64_SPECTRE_V3A);
712 }
713
714 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu);
715
kvm_arch_hardware_unsetup(void)716 static inline void kvm_arch_hardware_unsetup(void) {}
kvm_arch_sync_events(struct kvm * kvm)717 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
kvm_arch_sched_in(struct kvm_vcpu * vcpu,int cpu)718 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
kvm_arch_vcpu_block_finish(struct kvm_vcpu * vcpu)719 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
720
721 void kvm_arm_init_debug(void);
722 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu);
723 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
724 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
725 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
726 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
727 struct kvm_device_attr *attr);
728 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
729 struct kvm_device_attr *attr);
730 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
731 struct kvm_device_attr *attr);
732
733 /* Guest/host FPSIMD coordination helpers */
734 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
735 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
736 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
737 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
738
kvm_pmu_counter_deferred(struct perf_event_attr * attr)739 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
740 {
741 return (!has_vhe() && attr->exclude_host);
742 }
743
744 /* Flags for host debug state */
745 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
746 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
747
748 #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */
kvm_arch_vcpu_run_pid_change(struct kvm_vcpu * vcpu)749 static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
750 {
751 return kvm_arch_vcpu_run_map_fp(vcpu);
752 }
753
754 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
755 void kvm_clr_pmu_events(u32 clr);
756
757 void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
758 void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
759 #else
kvm_set_pmu_events(u32 set,struct perf_event_attr * attr)760 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
kvm_clr_pmu_events(u32 clr)761 static inline void kvm_clr_pmu_events(u32 clr) {}
762 #endif
763
764 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
765 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu);
766
767 int kvm_set_ipa_limit(void);
768
769 #define __KVM_HAVE_ARCH_VM_ALLOC
770 struct kvm *kvm_arch_alloc_vm(void);
771 void kvm_arch_free_vm(struct kvm *kvm);
772
773 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type);
774
775 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
776 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
777
778 #define kvm_arm_vcpu_sve_finalized(vcpu) \
779 ((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED)
780
781 #define kvm_vcpu_has_pmu(vcpu) \
782 (test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features))
783
784 #define kvm_supports_32bit_el0() \
785 (system_supports_32bit_el0() && \
786 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
787
788 int kvm_trng_call(struct kvm_vcpu *vcpu);
789 #ifdef CONFIG_KVM
790 extern phys_addr_t hyp_mem_base;
791 extern phys_addr_t hyp_mem_size;
792 void __init kvm_hyp_reserve(void);
793 #else
kvm_hyp_reserve(void)794 static inline void kvm_hyp_reserve(void) { }
795 #endif
796
797 #endif /* __ARM64_KVM_HOST_H__ */
798