1# SPDX-License-Identifier: GPL-2.0 2config XTENSA 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_BINFMT_FLAT if !MMU 6 select ARCH_HAS_DMA_PREP_COHERENT if MMU 7 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU 8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU 9 select ARCH_HAS_DMA_SET_UNCACHED if MMU 10 select ARCH_USE_QUEUED_RWLOCKS 11 select ARCH_USE_QUEUED_SPINLOCKS 12 select ARCH_WANT_FRAME_POINTERS 13 select ARCH_WANT_IPC_PARSE_VERSION 14 select BUILDTIME_TABLE_SORT 15 select CLONE_BACKWARDS 16 select COMMON_CLK 17 select DMA_REMAP if MMU 18 select GENERIC_ATOMIC64 19 select GENERIC_CLOCKEVENTS 20 select GENERIC_IRQ_SHOW 21 select GENERIC_PCI_IOMAP 22 select GENERIC_SCHED_CLOCK 23 select GENERIC_STRNCPY_FROM_USER if KASAN 24 select HAVE_ARCH_AUDITSYSCALL 25 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 26 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 27 select HAVE_ARCH_SECCOMP_FILTER 28 select HAVE_ARCH_TRACEHOOK 29 select HAVE_DEBUG_KMEMLEAK 30 select HAVE_DMA_CONTIGUOUS 31 select HAVE_EXIT_THREAD 32 select HAVE_FUNCTION_TRACER 33 select HAVE_FUTEX_CMPXCHG if !MMU && FUTEX 34 select HAVE_HW_BREAKPOINT if PERF_EVENTS 35 select HAVE_IRQ_TIME_ACCOUNTING 36 select HAVE_OPROFILE 37 select HAVE_PCI 38 select HAVE_PERF_EVENTS 39 select HAVE_STACKPROTECTOR 40 select HAVE_SYSCALL_TRACEPOINTS 41 select IRQ_DOMAIN 42 select MODULES_USE_ELF_RELA 43 select PERF_USE_VMALLOC 44 select SET_FS 45 select VIRT_TO_BUS 46 help 47 Xtensa processors are 32-bit RISC machines designed by Tensilica 48 primarily for embedded systems. These processors are both 49 configurable and extensible. The Linux port to the Xtensa 50 architecture supports all processor configurations and extensions, 51 with reasonable minimum requirements. The Xtensa Linux project has 52 a home page at <http://www.linux-xtensa.org/>. 53 54config GENERIC_HWEIGHT 55 def_bool y 56 57config ARCH_HAS_ILOG2_U32 58 def_bool n 59 60config ARCH_HAS_ILOG2_U64 61 def_bool n 62 63config NO_IOPORT_MAP 64 def_bool n 65 66config HZ 67 int 68 default 100 69 70config LOCKDEP_SUPPORT 71 def_bool y 72 73config STACKTRACE_SUPPORT 74 def_bool y 75 76config TRACE_IRQFLAGS_SUPPORT 77 def_bool y 78 79config MMU 80 def_bool n 81 82config HAVE_XTENSA_GPIO32 83 def_bool n 84 85config KASAN_SHADOW_OFFSET 86 hex 87 default 0x6e400000 88 89menu "Processor type and features" 90 91choice 92 prompt "Xtensa Processor Configuration" 93 default XTENSA_VARIANT_FSF 94 95config XTENSA_VARIANT_FSF 96 bool "fsf - default (not generic) configuration" 97 select MMU 98 99config XTENSA_VARIANT_DC232B 100 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 101 select MMU 102 select HAVE_XTENSA_GPIO32 103 help 104 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 105 106config XTENSA_VARIANT_DC233C 107 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 108 select MMU 109 select HAVE_XTENSA_GPIO32 110 help 111 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 112 113config XTENSA_VARIANT_CUSTOM 114 bool "Custom Xtensa processor configuration" 115 select HAVE_XTENSA_GPIO32 116 help 117 Select this variant to use a custom Xtensa processor configuration. 118 You will be prompted for a processor variant CORENAME. 119endchoice 120 121config XTENSA_VARIANT_CUSTOM_NAME 122 string "Xtensa Processor Custom Core Variant Name" 123 depends on XTENSA_VARIANT_CUSTOM 124 help 125 Provide the name of a custom Xtensa processor variant. 126 This CORENAME selects arch/xtensa/variant/CORENAME. 127 Don't forget you have to select MMU if you have one. 128 129config XTENSA_VARIANT_NAME 130 string 131 default "dc232b" if XTENSA_VARIANT_DC232B 132 default "dc233c" if XTENSA_VARIANT_DC233C 133 default "fsf" if XTENSA_VARIANT_FSF 134 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 135 136config XTENSA_VARIANT_MMU 137 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 138 depends on XTENSA_VARIANT_CUSTOM 139 default y 140 select MMU 141 help 142 Build a Conventional Kernel with full MMU support, 143 ie: it supports a TLB with auto-loading, page protection. 144 145config XTENSA_VARIANT_HAVE_PERF_EVENTS 146 bool "Core variant has Performance Monitor Module" 147 depends on XTENSA_VARIANT_CUSTOM 148 default n 149 help 150 Enable if core variant has Performance Monitor Module with 151 External Registers Interface. 152 153 If unsure, say N. 154 155config XTENSA_FAKE_NMI 156 bool "Treat PMM IRQ as NMI" 157 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 158 default n 159 help 160 If PMM IRQ is the only IRQ at EXCM level it is safe to 161 treat it as NMI, which improves accuracy of profiling. 162 163 If there are other interrupts at or above PMM IRQ priority level 164 but not above the EXCM level, PMM IRQ still may be treated as NMI, 165 but only if these IRQs are not used. There will be a build warning 166 saying that this is not safe, and a bugcheck if one of these IRQs 167 actually fire. 168 169 If unsure, say N. 170 171config XTENSA_UNALIGNED_USER 172 bool "Unaligned memory access in user space" 173 help 174 The Xtensa architecture currently does not handle unaligned 175 memory accesses in hardware but through an exception handler. 176 Per default, unaligned memory accesses are disabled in user space. 177 178 Say Y here to enable unaligned memory access in user space. 179 180config HAVE_SMP 181 bool "System Supports SMP (MX)" 182 depends on XTENSA_VARIANT_CUSTOM 183 select XTENSA_MX 184 help 185 This option is used to indicate that the system-on-a-chip (SOC) 186 supports Multiprocessing. Multiprocessor support implemented above 187 the CPU core definition and currently needs to be selected manually. 188 189 Multiprocessor support is implemented with external cache and 190 interrupt controllers. 191 192 The MX interrupt distributer adds Interprocessor Interrupts 193 and causes the IRQ numbers to be increased by 4 for devices 194 like the open cores ethernet driver and the serial interface. 195 196 You still have to select "Enable SMP" to enable SMP on this SOC. 197 198config SMP 199 bool "Enable Symmetric multi-processing support" 200 depends on HAVE_SMP 201 select GENERIC_SMP_IDLE_THREAD 202 help 203 Enabled SMP Software; allows more than one CPU/CORE 204 to be activated during startup. 205 206config NR_CPUS 207 depends on SMP 208 int "Maximum number of CPUs (2-32)" 209 range 2 32 210 default "4" 211 212config HOTPLUG_CPU 213 bool "Enable CPU hotplug support" 214 depends on SMP 215 help 216 Say Y here to allow turning CPUs off and on. CPUs can be 217 controlled through /sys/devices/system/cpu. 218 219 Say N if you want to disable CPU hotplug. 220 221config FAST_SYSCALL_XTENSA 222 bool "Enable fast atomic syscalls" 223 default n 224 help 225 fast_syscall_xtensa is a syscall that can make atomic operations 226 on UP kernel when processor has no s32c1i support. 227 228 This syscall is deprecated. It may have issues when called with 229 invalid arguments. It is provided only for backwards compatibility. 230 Only enable it if your userspace software requires it. 231 232 If unsure, say N. 233 234config FAST_SYSCALL_SPILL_REGISTERS 235 bool "Enable spill registers syscall" 236 default n 237 help 238 fast_syscall_spill_registers is a syscall that spills all active 239 register windows of a calling userspace task onto its stack. 240 241 This syscall is deprecated. It may have issues when called with 242 invalid arguments. It is provided only for backwards compatibility. 243 Only enable it if your userspace software requires it. 244 245 If unsure, say N. 246 247config USER_ABI_CALL0 248 bool 249 250choice 251 prompt "Userspace ABI" 252 default USER_ABI_DEFAULT 253 help 254 Select supported userspace ABI. 255 256 If unsure, choose the default ABI. 257 258config USER_ABI_DEFAULT 259 bool "Default ABI only" 260 help 261 Assume default userspace ABI. For XEA2 cores it is windowed ABI. 262 call0 ABI binaries may be run on such kernel, but signal delivery 263 will not work correctly for them. 264 265config USER_ABI_CALL0_ONLY 266 bool "Call0 ABI only" 267 select USER_ABI_CALL0 268 help 269 Select this option to support only call0 ABI in userspace. 270 Windowed ABI binaries will crash with a segfault caused by 271 an illegal instruction exception on the first 'entry' opcode. 272 273 Choose this option if you're planning to run only user code 274 built with call0 ABI. 275 276config USER_ABI_CALL0_PROBE 277 bool "Support both windowed and call0 ABI by probing" 278 select USER_ABI_CALL0 279 help 280 Select this option to support both windowed and call0 userspace 281 ABIs. When enabled all processes are started with PS.WOE disabled 282 and a fast user exception handler for an illegal instruction is 283 used to turn on PS.WOE bit on the first 'entry' opcode executed by 284 the userspace. 285 286 This option should be enabled for the kernel that must support 287 both call0 and windowed ABIs in userspace at the same time. 288 289 Note that Xtensa ISA does not guarantee that entry opcode will 290 raise an illegal instruction exception on cores with XEA2 when 291 PS.WOE is disabled, check whether the target core supports it. 292 293endchoice 294 295endmenu 296 297config XTENSA_CALIBRATE_CCOUNT 298 def_bool n 299 help 300 On some platforms (XT2000, for example), the CPU clock rate can 301 vary. The frequency can be determined, however, by measuring 302 against a well known, fixed frequency, such as an UART oscillator. 303 304config SERIAL_CONSOLE 305 def_bool n 306 307config PLATFORM_HAVE_XIP 308 def_bool n 309 310menu "Platform options" 311 312choice 313 prompt "Xtensa System Type" 314 default XTENSA_PLATFORM_ISS 315 316config XTENSA_PLATFORM_ISS 317 bool "ISS" 318 select XTENSA_CALIBRATE_CCOUNT 319 select SERIAL_CONSOLE 320 help 321 ISS is an acronym for Tensilica's Instruction Set Simulator. 322 323config XTENSA_PLATFORM_XT2000 324 bool "XT2000" 325 select HAVE_IDE 326 help 327 XT2000 is the name of Tensilica's feature-rich emulation platform. 328 This hardware is capable of running a full Linux distribution. 329 330config XTENSA_PLATFORM_XTFPGA 331 bool "XTFPGA" 332 select ETHOC if ETHERNET 333 select PLATFORM_WANT_DEFAULT_MEM if !MMU 334 select SERIAL_CONSOLE 335 select XTENSA_CALIBRATE_CCOUNT 336 select PLATFORM_HAVE_XIP 337 help 338 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 339 This hardware is capable of running a full Linux distribution. 340 341endchoice 342 343config PLATFORM_NR_IRQS 344 int 345 default 3 if XTENSA_PLATFORM_XT2000 346 default 0 347 348config XTENSA_CPU_CLOCK 349 int "CPU clock rate [MHz]" 350 depends on !XTENSA_CALIBRATE_CCOUNT 351 default 16 352 353config GENERIC_CALIBRATE_DELAY 354 bool "Auto calibration of the BogoMIPS value" 355 help 356 The BogoMIPS value can easily be derived from the CPU frequency. 357 358config CMDLINE_BOOL 359 bool "Default bootloader kernel arguments" 360 361config CMDLINE 362 string "Initial kernel command string" 363 depends on CMDLINE_BOOL 364 default "console=ttyS0,38400 root=/dev/ram" 365 help 366 On some architectures (EBSA110 and CATS), there is currently no way 367 for the boot loader to pass arguments to the kernel. For these 368 architectures, you should supply some command-line options at build 369 time by entering them here. As a minimum, you should specify the 370 memory size and the root device (e.g., mem=64M root=/dev/nfs). 371 372config USE_OF 373 bool "Flattened Device Tree support" 374 select OF 375 select OF_EARLY_FLATTREE 376 help 377 Include support for flattened device tree machine descriptions. 378 379config BUILTIN_DTB_SOURCE 380 string "DTB to build into the kernel image" 381 depends on OF 382 383config PARSE_BOOTPARAM 384 bool "Parse bootparam block" 385 default y 386 help 387 Parse parameters passed to the kernel from the bootloader. It may 388 be disabled if the kernel is known to run without the bootloader. 389 390 If unsure, say Y. 391 392config BLK_DEV_SIMDISK 393 tristate "Host file-based simulated block device support" 394 default n 395 depends on XTENSA_PLATFORM_ISS && BLOCK 396 help 397 Create block devices that map to files in the host file system. 398 Device binding to host file may be changed at runtime via proc 399 interface provided the device is not in use. 400 401config BLK_DEV_SIMDISK_COUNT 402 int "Number of host file-based simulated block devices" 403 range 1 10 404 depends on BLK_DEV_SIMDISK 405 default 2 406 help 407 This is the default minimal number of created block devices. 408 Kernel/module parameter 'simdisk_count' may be used to change this 409 value at runtime. More file names (but no more than 10) may be 410 specified as parameters, simdisk_count grows accordingly. 411 412config SIMDISK0_FILENAME 413 string "Host filename for the first simulated device" 414 depends on BLK_DEV_SIMDISK = y 415 default "" 416 help 417 Attach a first simdisk to a host file. Conventionally, this file 418 contains a root file system. 419 420config SIMDISK1_FILENAME 421 string "Host filename for the second simulated device" 422 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 423 default "" 424 help 425 Another simulated disk in a host file for a buildroot-independent 426 storage. 427 428config XTFPGA_LCD 429 bool "Enable XTFPGA LCD driver" 430 depends on XTENSA_PLATFORM_XTFPGA 431 default n 432 help 433 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 434 progress messages there during bootup/shutdown. It may be useful 435 during board bringup. 436 437 If unsure, say N. 438 439config XTFPGA_LCD_BASE_ADDR 440 hex "XTFPGA LCD base address" 441 depends on XTFPGA_LCD 442 default "0x0d0c0000" 443 help 444 Base address of the LCD controller inside KIO region. 445 Different boards from XTFPGA family have LCD controller at different 446 addresses. Please consult prototyping user guide for your board for 447 the correct address. Wrong address here may lead to hardware lockup. 448 449config XTFPGA_LCD_8BIT_ACCESS 450 bool "Use 8-bit access to XTFPGA LCD" 451 depends on XTFPGA_LCD 452 default n 453 help 454 LCD may be connected with 4- or 8-bit interface, 8-bit access may 455 only be used with 8-bit interface. Please consult prototyping user 456 guide for your board for the correct interface width. 457 458comment "Kernel memory layout" 459 460config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 461 bool "Initialize Xtensa MMU inside the Linux kernel code" 462 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 463 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 464 help 465 Earlier version initialized the MMU in the exception vector 466 before jumping to _startup in head.S and had an advantage that 467 it was possible to place a software breakpoint at 'reset' and 468 then enter your normal kernel breakpoints once the MMU was mapped 469 to the kernel mappings (0XC0000000). 470 471 This unfortunately won't work for U-Boot and likely also wont 472 work for using KEXEC to have a hot kernel ready for doing a 473 KDUMP. 474 475 So now the MMU is initialized in head.S but it's necessary to 476 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 477 xt-gdb can't place a Software Breakpoint in the 0XD region prior 478 to mapping the MMU and after mapping even if the area of low memory 479 was mapped gdb wouldn't remove the breakpoint on hitting it as the 480 PC wouldn't match. Since Hardware Breakpoints are recommended for 481 Linux configurations it seems reasonable to just assume they exist 482 and leave this older mechanism for unfortunate souls that choose 483 not to follow Tensilica's recommendation. 484 485 Selecting this will cause U-Boot to set the KERNEL Load and Entry 486 address at 0x00003000 instead of the mapped std of 0xD0003000. 487 488 If in doubt, say Y. 489 490config XIP_KERNEL 491 bool "Kernel Execute-In-Place from ROM" 492 depends on PLATFORM_HAVE_XIP 493 help 494 Execute-In-Place allows the kernel to run from non-volatile storage 495 directly addressable by the CPU, such as NOR flash. This saves RAM 496 space since the text section of the kernel is not loaded from flash 497 to RAM. Read-write sections, such as the data section and stack, 498 are still copied to RAM. The XIP kernel is not compressed since 499 it has to run directly from flash, so it will take more space to 500 store it. The flash address used to link the kernel object files, 501 and for storing it, is configuration dependent. Therefore, if you 502 say Y here, you must know the proper physical address where to 503 store the kernel image depending on your own flash memory usage. 504 505 Also note that the make target becomes "make xipImage" rather than 506 "make Image" or "make uImage". The final kernel binary to put in 507 ROM memory will be arch/xtensa/boot/xipImage. 508 509 If unsure, say N. 510 511config MEMMAP_CACHEATTR 512 hex "Cache attributes for the memory address space" 513 depends on !MMU 514 default 0x22222222 515 help 516 These cache attributes are set up for noMMU systems. Each hex digit 517 specifies cache attributes for the corresponding 512MB memory 518 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 519 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 520 521 Cache attribute values are specific for the MMU type. 522 For region protection MMUs: 523 1: WT cached, 524 2: cache bypass, 525 4: WB cached, 526 f: illegal. 527 For full MMU: 528 bit 0: executable, 529 bit 1: writable, 530 bits 2..3: 531 0: cache bypass, 532 1: WB cache, 533 2: WT cache, 534 3: special (c and e are illegal, f is reserved). 535 For MPU: 536 0: illegal, 537 1: WB cache, 538 2: WB, no-write-allocate cache, 539 3: WT cache, 540 4: cache bypass. 541 542config KSEG_PADDR 543 hex "Physical address of the KSEG mapping" 544 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 545 default 0x00000000 546 help 547 This is the physical address where KSEG is mapped. Please refer to 548 the chosen KSEG layout help for the required address alignment. 549 Unpacked kernel image (including vectors) must be located completely 550 within KSEG. 551 Physical memory below this address is not available to linux. 552 553 If unsure, leave the default value here. 554 555config KERNEL_VIRTUAL_ADDRESS 556 hex "Kernel virtual address" 557 depends on MMU && XIP_KERNEL 558 default 0xd0003000 559 help 560 This is the virtual address where the XIP kernel is mapped. 561 XIP kernel may be mapped into KSEG or KIO region, virtual address 562 provided here must match kernel load address provided in 563 KERNEL_LOAD_ADDRESS. 564 565config KERNEL_LOAD_ADDRESS 566 hex "Kernel load address" 567 default 0x60003000 if !MMU 568 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 569 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 570 help 571 This is the address where the kernel is loaded. 572 It is virtual address for MMUv2 configurations and physical address 573 for all other configurations. 574 575 If unsure, leave the default value here. 576 577choice 578 prompt "Relocatable vectors location" 579 default XTENSA_VECTORS_IN_TEXT 580 help 581 Choose whether relocatable vectors are merged into the kernel .text 582 or placed separately at runtime. This option does not affect 583 configurations without VECBASE register where vectors are always 584 placed at their hardware-defined locations. 585 586config XTENSA_VECTORS_IN_TEXT 587 bool "Merge relocatable vectors into kernel text" 588 depends on !MTD_XIP 589 help 590 This option puts relocatable vectors into the kernel .text section 591 with proper alignment. 592 This is a safe choice for most configurations. 593 594config XTENSA_VECTORS_SEPARATE 595 bool "Put relocatable vectors at fixed address" 596 help 597 This option puts relocatable vectors at specific virtual address. 598 Vectors are merged with the .init data in the kernel image and 599 are copied into their designated location during kernel startup. 600 Use it to put vectors into IRAM or out of FLASH on kernels with 601 XIP-aware MTD support. 602 603endchoice 604 605config VECTORS_ADDR 606 hex "Kernel vectors virtual address" 607 default 0x00000000 608 depends on XTENSA_VECTORS_SEPARATE 609 help 610 This is the virtual address of the (relocatable) vectors base. 611 It must be within KSEG if MMU is used. 612 613config XIP_DATA_ADDR 614 hex "XIP kernel data virtual address" 615 depends on XIP_KERNEL 616 default 0x00000000 617 help 618 This is the virtual address where XIP kernel data is copied. 619 It must be within KSEG if MMU is used. 620 621config PLATFORM_WANT_DEFAULT_MEM 622 def_bool n 623 624config DEFAULT_MEM_START 625 hex 626 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 627 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 628 default 0x00000000 629 help 630 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 631 in noMMU configurations. 632 633 If unsure, leave the default value here. 634 635choice 636 prompt "KSEG layout" 637 depends on MMU 638 default XTENSA_KSEG_MMU_V2 639 640config XTENSA_KSEG_MMU_V2 641 bool "MMUv2: 128MB cached + 128MB uncached" 642 help 643 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 644 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 645 without cache. 646 KSEG_PADDR must be aligned to 128MB. 647 648config XTENSA_KSEG_256M 649 bool "256MB cached + 256MB uncached" 650 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 651 help 652 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 653 with cache and to 0xc0000000 without cache. 654 KSEG_PADDR must be aligned to 256MB. 655 656config XTENSA_KSEG_512M 657 bool "512MB cached + 512MB uncached" 658 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 659 help 660 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 661 with cache and to 0xc0000000 without cache. 662 KSEG_PADDR must be aligned to 256MB. 663 664endchoice 665 666config HIGHMEM 667 bool "High Memory Support" 668 depends on MMU 669 help 670 Linux can use the full amount of RAM in the system by 671 default. However, the default MMUv2 setup only maps the 672 lowermost 128 MB of memory linearly to the areas starting 673 at 0xd0000000 (cached) and 0xd8000000 (uncached). 674 When there are more than 128 MB memory in the system not 675 all of it can be "permanently mapped" by the kernel. 676 The physical memory that's not permanently mapped is called 677 "high memory". 678 679 If you are compiling a kernel which will never run on a 680 machine with more than 128 MB total physical RAM, answer 681 N here. 682 683 If unsure, say Y. 684 685config FORCE_MAX_ZONEORDER 686 int "Maximum zone order" 687 default "11" 688 help 689 The kernel memory allocator divides physically contiguous memory 690 blocks into "zones", where each zone is a power of two number of 691 pages. This option selects the largest power of two that the kernel 692 keeps in the memory allocator. If you need to allocate very large 693 blocks of physically contiguous memory, then you may need to 694 increase this value. 695 696 This config option is actually maximum order plus one. For example, 697 a value of 11 means that the largest free memory block is 2^10 pages. 698 699endmenu 700 701menu "Power management options" 702 703source "kernel/power/Kconfig" 704 705endmenu 706