1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 9 #ifndef __HALDMOUTSRC_H__ 10 #define __HALDMOUTSRC_H__ 11 12 #include "odm_EdcaTurboCheck.h" 13 #include "odm_DIG.h" 14 #include "odm_PathDiv.h" 15 #include "odm_DynamicBBPowerSaving.h" 16 #include "odm_DynamicTxPower.h" 17 #include "odm_CfoTracking.h" 18 #include "odm_NoiseMonitor.h" 19 20 #define TP_MODE 0 21 #define RSSI_MODE 1 22 #define TRAFFIC_LOW 0 23 #define TRAFFIC_HIGH 1 24 #define NONE 0 25 26 /* 3 Tx Power Tracking */ 27 /* 3 ============================================================ */ 28 #define DPK_DELTA_MAPPING_NUM 13 29 #define index_mapping_HP_NUM 15 30 #define OFDM_TABLE_SIZE 43 31 #define CCK_TABLE_SIZE 33 32 #define TXSCALE_TABLE_SIZE 37 33 #define TXPWR_TRACK_TABLE_SIZE 30 34 #define DELTA_SWINGIDX_SIZE 30 35 #define BAND_NUM 4 36 37 /* 3 PSD Handler */ 38 /* 3 ============================================================ */ 39 40 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 41 #define MODE_40M 0 /* 0:20M, 1:40M */ 42 #define PSD_TH2 3 43 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 44 #define SIR_STEP_SIZE 3 45 #define Smooth_Size_1 5 46 #define Smooth_TH_1 3 47 #define Smooth_Size_2 10 48 #define Smooth_TH_2 4 49 #define Smooth_Size_3 20 50 #define Smooth_TH_3 4 51 #define Smooth_Step_Size 5 52 #define Adaptive_SIR 1 53 #define PSD_RESCAN 4 54 #define PSD_SCAN_INTERVAL 700 /* ms */ 55 56 /* 8723A High Power IGI Setting */ 57 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 58 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 59 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 60 #define DM_DIG_LOW_PWR_THRESHOLD 0x14 61 62 /* ANT Test */ 63 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 64 #define ANTTESTA 0x01 /* Ant A will be Testing */ 65 #define ANTTESTB 0x02 /* Ant B will be testing */ 66 67 #define PS_MODE_ACTIVE 0x01 68 69 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */ 70 #define MAIN_ANT 1 /* Ant A or Ant Main */ 71 #define AUX_ANT 2 /* AntB or Ant Aux */ 72 #define MAX_ANT 3 /* 3 for AP using */ 73 74 /* Antenna Diversity Type */ 75 #define SW_ANTDIV 0 76 #define HW_ANTDIV 1 77 /* structure and define */ 78 79 /* Remove DIG by Yuchen */ 80 81 /* Remoce BB power saving by Yuchn */ 82 83 /* Remove DIG by yuchen */ 84 85 struct dynamic_primary_CCA { 86 u8 PriCCA_flag; 87 u8 intf_flag; 88 u8 intf_type; 89 u8 DupRTS_flag; 90 u8 Monitor_flag; 91 u8 CH_offset; 92 u8 MF_state; 93 }; 94 95 typedef struct _Rate_Adaptive_Table_ { 96 u8 firstconnect; 97 } RA_T, *pRA_T; 98 99 typedef struct _RX_High_Power_ { 100 u8 RXHP_flag; 101 u8 PSD_func_trigger; 102 u8 PSD_bitmap_RXHP[80]; 103 u8 Pre_IGI; 104 u8 Cur_IGI; 105 u8 Pre_pw_th; 106 u8 Cur_pw_th; 107 bool First_time_enter; 108 bool RXHP_enable; 109 u8 TP_Mode; 110 RT_TIMER PSDTimer; 111 } RXHP_T, *pRXHP_T; 112 113 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 114 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 115 116 /* This indicates two different the steps. */ 117 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 118 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 119 /* with original RSSI to determine if it is necessary to switch antenna. */ 120 #define SWAW_STEP_PEAK 0 121 #define SWAW_STEP_DETERMINE 1 122 123 #define TP_MODE 0 124 #define RSSI_MODE 1 125 #define TRAFFIC_LOW 0 126 #define TRAFFIC_HIGH 1 127 #define TRAFFIC_UltraLOW 2 128 129 typedef struct _SW_Antenna_Switch_ { 130 u8 Double_chk_flag; 131 u8 try_flag; 132 s32 PreRSSI; 133 u8 CurAntenna; 134 u8 PreAntenna; 135 u8 RSSI_Trying; 136 u8 TestMode; 137 u8 bTriggerAntennaSwitch; 138 u8 SelectAntennaMap; 139 u8 RSSI_target; 140 u8 reset_idx; 141 u16 Single_Ant_Counter; 142 u16 Dual_Ant_Counter; 143 u16 Aux_FailDetec_Counter; 144 u16 Retry_Counter; 145 146 /* Before link Antenna Switch check */ 147 u8 SWAS_NoLink_State; 148 u32 SWAS_NoLink_BK_Reg860; 149 u32 SWAS_NoLink_BK_Reg92c; 150 u32 SWAS_NoLink_BK_Reg948; 151 bool ANTA_ON; /* To indicate Ant A is or not */ 152 bool ANTB_ON; /* To indicate Ant B is on or not */ 153 bool Pre_Aux_FailDetec; 154 bool RSSI_AntDect_bResult; 155 u8 Ant5G; 156 u8 Ant2G; 157 158 s32 RSSI_sum_A; 159 s32 RSSI_sum_B; 160 s32 RSSI_cnt_A; 161 s32 RSSI_cnt_B; 162 163 u64 lastTxOkCnt; 164 u64 lastRxOkCnt; 165 u64 TXByteCnt_A; 166 u64 TXByteCnt_B; 167 u64 RXByteCnt_A; 168 u64 RXByteCnt_B; 169 u8 TrafficLoad; 170 u8 Train_time; 171 u8 Train_time_flag; 172 RT_TIMER SwAntennaSwitchTimer; 173 RT_TIMER SwAntennaSwitchTimer_8723B; 174 u32 PktCnt_SWAntDivByCtrlFrame; 175 bool bSWAntDivByCtrlFrame; 176 } SWAT_T, *pSWAT_T; 177 178 /* Remove Edca by YuChen */ 179 180 181 typedef struct _ODM_RATE_ADAPTIVE { 182 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 183 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */ 184 bool bUseLdpc; 185 bool bLowerRtsRate; 186 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 187 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 188 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 189 190 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; 191 192 #define IQK_MAC_REG_NUM 4 193 #define IQK_ADDA_REG_NUM 16 194 #define IQK_BB_REG_NUM_MAX 10 195 #define IQK_BB_REG_NUM 9 196 #define HP_THERMAL_NUM 8 197 198 #define AVG_THERMAL_NUM 8 199 #define IQK_Matrix_REG_NUM 8 200 #define IQK_Matrix_Settings_NUM 14 /* Channels_2_4G_NUM */ 201 202 #define DM_Type_ByFW 0 203 #define DM_Type_ByDriver 1 204 205 /* */ 206 /* Declare for common info */ 207 /* */ 208 #define MAX_PATH_NUM_92CS 2 209 #define MAX_PATH_NUM_8188E 1 210 #define MAX_PATH_NUM_8192E 2 211 #define MAX_PATH_NUM_8723B 1 212 #define MAX_PATH_NUM_8812A 2 213 #define MAX_PATH_NUM_8821A 1 214 #define MAX_PATH_NUM_8814A 4 215 #define MAX_PATH_NUM_8822B 2 216 217 #define IQK_THRESHOLD 8 218 #define DPK_THRESHOLD 4 219 220 struct odm_phy_info { 221 /* 222 * Be care, if you want to add any element, please insert it between 223 * rx_pwd_ball and signal_strength. 224 */ 225 u8 rx_pwd_ba11; 226 227 u8 signal_quality; /* in 0-100 index. */ 228 s8 rx_mimo_signal_quality[4]; /* per-path's EVM */ 229 u8 rx_mimo_evm_dbm[4]; /* per-path's EVM dbm */ 230 231 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ 232 233 u16 cfo_short[4]; /* per-path's Cfo_short */ 234 u16 cfo_tail[4]; /* per-path's Cfo_tail */ 235 236 s8 rx_power; /* in dBm Translate from PWdB */ 237 238 /* 239 * Real power in dBm for this packet, no beautification and 240 * aggregation. Keep this raw info to be used for the other procedures. 241 */ 242 s8 recv_signal_power; 243 u8 bt_rx_rssi_percentage; 244 u8 signal_strength; /* in 0-100 index. */ 245 246 s8 rx_pwr[4]; /* per-path's pwdb */ 247 248 u8 rx_snr[4]; /* per-path's SNR */ 249 u8 band_width; 250 u8 bt_coex_pwr_adjust; 251 }; 252 253 struct odm_packet_info { 254 u8 data_rate; 255 u8 station_id; 256 bool bssid_match; 257 bool to_self; 258 bool is_beacon; 259 }; 260 261 struct odm_phy_dbg_info { 262 /* ODM Write, debug info */ 263 s8 RxSNRdB[4]; 264 u32 NumQryPhyStatus; 265 u32 NumQryPhyStatusCCK; 266 u32 NumQryPhyStatusOFDM; 267 u8 NumQryBeaconPkt; 268 /* Others */ 269 s32 RxEVM[4]; 270 271 }; 272 273 struct odm_mac_status_info { 274 u8 test; 275 }; 276 277 typedef enum tag_Dynamic_ODM_Support_Ability_Type { 278 /* BB Team */ 279 ODM_DIG = 0x00000001, 280 ODM_HIGH_POWER = 0x00000002, 281 ODM_CCK_CCA_TH = 0x00000004, 282 ODM_FA_STATISTICS = 0x00000008, 283 ODM_RAMASK = 0x00000010, 284 ODM_RSSI_MONITOR = 0x00000020, 285 ODM_SW_ANTDIV = 0x00000040, 286 ODM_HW_ANTDIV = 0x00000080, 287 ODM_BB_PWRSV = 0x00000100, 288 ODM_2TPATHDIV = 0x00000200, 289 ODM_1TPATHDIV = 0x00000400, 290 ODM_PSD2AFH = 0x00000800 291 } ODM_Ability_E; 292 293 /* */ 294 /* 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T */ 295 /* Please declare below ODM relative info in your STA info structure. */ 296 /* */ 297 typedef struct _ODM_STA_INFO { 298 /* Driver Write */ 299 bool bUsed; /* record the sta status link or not? */ 300 /* u8 WirelessMode; */ 301 u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ 302 303 /* ODM Write */ 304 /* 1 PHY_STATUS_INFO */ 305 u8 RSSI_Path[4]; /* */ 306 u8 RSSI_Ave; 307 u8 RXEVM[4]; 308 u8 RXSNR[4]; 309 310 /* ODM Write */ 311 /* 1 TX_INFO (may changed by IC) */ 312 /* TX_INFO_T pTxInfo; Define in IC folder. Move lower layer. */ 313 314 /* */ 315 /* Please use compile flag to disabe the strcutrue for other IC except 88E. */ 316 /* Move To lower layer. */ 317 /* */ 318 /* ODM Write Wilson will handle this part(said by Luke.Lee) */ 319 /* TX_RPT_T pTxRpt; Define in IC folder. Move lower layer. */ 320 } ODM_STA_INFO_T, *PODM_STA_INFO_T; 321 322 /* */ 323 /* 2011/10/20 MH Define Common info enum for all team. */ 324 /* */ 325 typedef enum _ODM_Common_Info_Definition { 326 /* Fixed value: */ 327 328 /* HOOK BEFORE REG INIT----------- */ 329 ODM_CMNINFO_PLATFORM = 0, 330 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 331 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ 332 ODM_CMNINFO_MP_TEST_CHIP, 333 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ 334 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ 335 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ 336 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ 337 ODM_CMNINFO_RFE_TYPE, 338 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ 339 ODM_CMNINFO_PACKAGE_TYPE, 340 ODM_CMNINFO_EXT_LNA, /* true */ 341 ODM_CMNINFO_5G_EXT_LNA, 342 ODM_CMNINFO_EXT_PA, 343 ODM_CMNINFO_5G_EXT_PA, 344 ODM_CMNINFO_GPA, 345 ODM_CMNINFO_APA, 346 ODM_CMNINFO_GLNA, 347 ODM_CMNINFO_ALNA, 348 ODM_CMNINFO_EXT_TRSW, 349 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 350 ODM_CMNINFO_BINHCT_TEST, 351 ODM_CMNINFO_BWIFI_TEST, 352 ODM_CMNINFO_SMART_CONCURRENT, 353 /* HOOK BEFORE REG INIT----------- */ 354 355 /* Dynamic value: */ 356 /* POINTER REFERENCE----------- */ 357 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ 358 ODM_CMNINFO_TX_UNI, 359 ODM_CMNINFO_RX_UNI, 360 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 361 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */ 362 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 363 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 364 ODM_CMNINFO_BW, /* ODM_BW_E */ 365 ODM_CMNINFO_CHNL, 366 ODM_CMNINFO_FORCED_RATE, 367 368 ODM_CMNINFO_DMSP_GET_VALUE, 369 ODM_CMNINFO_BUDDY_ADAPTOR, 370 ODM_CMNINFO_DMSP_IS_MASTER, 371 ODM_CMNINFO_SCAN, 372 ODM_CMNINFO_POWER_SAVING, 373 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ 374 ODM_CMNINFO_DRV_STOP, 375 ODM_CMNINFO_PNP_IN, 376 ODM_CMNINFO_INIT_ON, 377 ODM_CMNINFO_ANT_TEST, 378 ODM_CMNINFO_NET_CLOSED, 379 ODM_CMNINFO_MP_MODE, 380 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */ 381 ODM_CMNINFO_FORCED_IGI_LB, 382 ODM_CMNINFO_IS1ANTENNA, 383 ODM_CMNINFO_RFDEFAULTPATH, 384 /* POINTER REFERENCE----------- */ 385 386 /* CALL BY VALUE------------- */ 387 ODM_CMNINFO_WIFI_DIRECT, 388 ODM_CMNINFO_WIFI_DISPLAY, 389 ODM_CMNINFO_LINK_IN_PROGRESS, 390 ODM_CMNINFO_LINK, 391 ODM_CMNINFO_STATION_STATE, 392 ODM_CMNINFO_RSSI_MIN, 393 ODM_CMNINFO_DBG_COMP, /* u64 */ 394 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 395 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 396 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 397 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 398 ODM_CMNINFO_BT_ENABLED, 399 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 400 ODM_CMNINFO_BT_HS_RSSI, 401 ODM_CMNINFO_BT_OPERATION, 402 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */ 403 ODM_CMNINFO_BT_DISABLE_EDCA, 404 /* CALL BY VALUE------------- */ 405 406 /* Dynamic ptr array hook itms. */ 407 ODM_CMNINFO_STA_STATUS, 408 ODM_CMNINFO_PHY_STATUS, 409 ODM_CMNINFO_MAC_STATUS, 410 411 ODM_CMNINFO_MAX, 412 } ODM_CMNINFO_E; 413 414 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 415 typedef enum _ODM_Support_Ability_Definition { 416 /* */ 417 /* BB ODM section BIT 0-15 */ 418 /* */ 419 ODM_BB_DIG = BIT0, 420 ODM_BB_RA_MASK = BIT1, 421 ODM_BB_DYNAMIC_TXPWR = BIT2, 422 ODM_BB_FA_CNT = BIT3, 423 ODM_BB_RSSI_MONITOR = BIT4, 424 ODM_BB_CCK_PD = BIT5, 425 ODM_BB_ANT_DIV = BIT6, 426 ODM_BB_PWR_SAVE = BIT7, 427 ODM_BB_PWR_TRAIN = BIT8, 428 ODM_BB_RATE_ADAPTIVE = BIT9, 429 ODM_BB_PATH_DIV = BIT10, 430 ODM_BB_PSD = BIT11, 431 ODM_BB_RXHP = BIT12, 432 ODM_BB_ADAPTIVITY = BIT13, 433 ODM_BB_CFO_TRACKING = BIT14, 434 435 /* MAC DM section BIT 16-23 */ 436 ODM_MAC_EDCA_TURBO = BIT16, 437 ODM_MAC_EARLY_MODE = BIT17, 438 439 /* RF ODM section BIT 24-31 */ 440 ODM_RF_TX_PWR_TRACK = BIT24, 441 ODM_RF_RX_GAIN_TRACK = BIT25, 442 ODM_RF_CALIBRATION = BIT26, 443 } ODM_ABILITY_E; 444 445 /* ODM_CMNINFO_INTERFACE */ 446 typedef enum tag_ODM_Support_Interface_Definition { 447 ODM_ITRF_SDIO = 0x4, 448 ODM_ITRF_ALL = 0x7, 449 } ODM_INTERFACE_E; 450 451 /* ODM_CMNINFO_IC_TYPE */ 452 typedef enum tag_ODM_Support_IC_Type_Definition { 453 ODM_RTL8723B = BIT8, 454 } ODM_IC_TYPE_E; 455 456 /* ODM_CMNINFO_CUT_VER */ 457 typedef enum tag_ODM_Cut_Version_Definition { 458 ODM_CUT_A = 0, 459 ODM_CUT_B = 1, 460 ODM_CUT_C = 2, 461 ODM_CUT_D = 3, 462 ODM_CUT_E = 4, 463 ODM_CUT_F = 5, 464 465 ODM_CUT_I = 8, 466 ODM_CUT_J = 9, 467 ODM_CUT_K = 10, 468 ODM_CUT_TEST = 15, 469 } ODM_CUT_VERSION_E; 470 471 /* ODM_CMNINFO_FAB_VER */ 472 typedef enum tag_ODM_Fab_Version_Definition { 473 ODM_TSMC = 0, 474 ODM_UMC = 1, 475 } ODM_FAB_E; 476 477 /* ODM_CMNINFO_RF_TYPE */ 478 /* */ 479 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 480 /* */ 481 typedef enum tag_ODM_RF_Path_Bit_Definition { 482 ODM_RF_TX_A = BIT0, 483 ODM_RF_TX_B = BIT1, 484 ODM_RF_TX_C = BIT2, 485 ODM_RF_TX_D = BIT3, 486 ODM_RF_RX_A = BIT4, 487 ODM_RF_RX_B = BIT5, 488 ODM_RF_RX_C = BIT6, 489 ODM_RF_RX_D = BIT7, 490 } ODM_RF_PATH_E; 491 492 typedef enum tag_ODM_RF_Type_Definition { 493 ODM_1T1R = 0, 494 ODM_1T2R = 1, 495 ODM_2T2R = 2, 496 ODM_2T3R = 3, 497 ODM_2T4R = 4, 498 ODM_3T3R = 5, 499 ODM_3T4R = 6, 500 ODM_4T4R = 7, 501 } ODM_RF_TYPE_E; 502 503 /* */ 504 /* ODM Dynamic common info value definition */ 505 /* */ 506 507 /* typedef enum _MACPHY_MODE_8192D{ */ 508 /* SINGLEMAC_SINGLEPHY, */ 509 /* DUALMAC_DUALPHY, */ 510 /* DUALMAC_SINGLEPHY, */ 511 /* MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; */ 512 /* Above is the original define in MP driver. Please use the same define. THX. */ 513 typedef enum tag_ODM_MAC_PHY_Mode_Definition { 514 ODM_SMSP = 0, 515 ODM_DMSP = 1, 516 ODM_DMDP = 2, 517 } ODM_MAC_PHY_MODE_E; 518 519 typedef enum tag_BT_Coexist_Definition { 520 ODM_BT_BUSY = 1, 521 ODM_BT_ON = 2, 522 ODM_BT_OFF = 3, 523 ODM_BT_NONE = 4, 524 } ODM_BT_COEXIST_E; 525 526 /* ODM_CMNINFO_OP_MODE */ 527 typedef enum tag_Operation_Mode_Definition { 528 ODM_NO_LINK = BIT0, 529 ODM_LINK = BIT1, 530 ODM_SCAN = BIT2, 531 ODM_POWERSAVE = BIT3, 532 ODM_AP_MODE = BIT4, 533 ODM_CLIENT_MODE = BIT5, 534 ODM_AD_HOC = BIT6, 535 ODM_WIFI_DIRECT = BIT7, 536 ODM_WIFI_DISPLAY = BIT8, 537 } ODM_OPERATION_MODE_E; 538 539 /* ODM_CMNINFO_WM_MODE */ 540 typedef enum tag_Wireless_Mode_Definition { 541 ODM_WM_UNKNOWN = 0x0, 542 ODM_WM_B = BIT0, 543 ODM_WM_G = BIT1, 544 ODM_WM_A = BIT2, 545 ODM_WM_N24G = BIT3, 546 ODM_WM_N5G = BIT4, 547 ODM_WM_AUTO = BIT5, 548 ODM_WM_AC = BIT6, 549 } ODM_WIRELESS_MODE_E; 550 551 /* ODM_CMNINFO_BAND */ 552 typedef enum tag_Band_Type_Definition { 553 ODM_BAND_2_4G = 0, 554 ODM_BAND_5G, 555 ODM_BAND_ON_BOTH, 556 ODM_BANDMAX 557 } ODM_BAND_TYPE_E; 558 559 /* ODM_CMNINFO_SEC_CHNL_OFFSET */ 560 typedef enum tag_Secondary_Channel_Offset_Definition { 561 ODM_DONT_CARE = 0, 562 ODM_BELOW = 1, 563 ODM_ABOVE = 2 564 } ODM_SEC_CHNL_OFFSET_E; 565 566 /* ODM_CMNINFO_SEC_MODE */ 567 typedef enum tag_Security_Definition { 568 ODM_SEC_OPEN = 0, 569 ODM_SEC_WEP40 = 1, 570 ODM_SEC_TKIP = 2, 571 ODM_SEC_RESERVE = 3, 572 ODM_SEC_AESCCMP = 4, 573 ODM_SEC_WEP104 = 5, 574 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ 575 ODM_SEC_SMS4 = 7, 576 } ODM_SECURITY_E; 577 578 /* ODM_CMNINFO_BW */ 579 typedef enum tag_Bandwidth_Definition { 580 ODM_BW20M = 0, 581 ODM_BW40M = 1, 582 ODM_BW80M = 2, 583 ODM_BW160M = 3, 584 ODM_BW10M = 4, 585 } ODM_BW_E; 586 587 /* ODM_CMNINFO_BOARD_TYPE */ 588 /* For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored */ 589 /* For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G */ 590 typedef enum tag_Board_Definition { 591 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ 592 ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */ 593 ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ 594 ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */ 595 ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */ 596 ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ 597 ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */ 598 ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */ 599 ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ 600 } ODM_BOARD_TYPE_E; 601 602 typedef enum tag_ODM_Package_Definition { 603 ODM_PACKAGE_DEFAULT = 0, 604 ODM_PACKAGE_QFN68 = BIT(0), 605 ODM_PACKAGE_TFBGA90 = BIT(1), 606 ODM_PACKAGE_TFBGA79 = BIT(2), 607 } ODM_Package_TYPE_E; 608 609 typedef enum tag_ODM_TYPE_GPA_Definition { 610 TYPE_GPA0 = 0, 611 TYPE_GPA1 = BIT(1)|BIT(0) 612 } ODM_TYPE_GPA_E; 613 614 typedef enum tag_ODM_TYPE_APA_Definition { 615 TYPE_APA0 = 0, 616 TYPE_APA1 = BIT(1)|BIT(0) 617 } ODM_TYPE_APA_E; 618 619 typedef enum tag_ODM_TYPE_GLNA_Definition { 620 TYPE_GLNA0 = 0, 621 TYPE_GLNA1 = BIT(2)|BIT(0), 622 TYPE_GLNA2 = BIT(3)|BIT(1), 623 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 624 } ODM_TYPE_GLNA_E; 625 626 typedef enum tag_ODM_TYPE_ALNA_Definition { 627 TYPE_ALNA0 = 0, 628 TYPE_ALNA1 = BIT(2)|BIT(0), 629 TYPE_ALNA2 = BIT(3)|BIT(1), 630 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 631 } ODM_TYPE_ALNA_E; 632 633 /* ODM_CMNINFO_ONE_PATH_CCA */ 634 typedef enum tag_CCA_Path { 635 ODM_CCA_2R = 0, 636 ODM_CCA_1R_A = 1, 637 ODM_CCA_1R_B = 2, 638 } ODM_CCA_PATH_E; 639 640 typedef struct _ODM_RA_Info_ { 641 u8 RateID; 642 u32 RateMask; 643 u32 RAUseRate; 644 u8 RateSGI; 645 u8 RssiStaRA; 646 u8 PreRssiStaRA; 647 u8 SGIEnable; 648 u8 DecisionRate; 649 u8 PreRate; 650 u8 HighestRate; 651 u8 LowestRate; 652 u32 NscUp; 653 u32 NscDown; 654 u16 RTY[5]; 655 u32 TOTAL; 656 u16 DROP; 657 u8 Active; 658 u16 RptTime; 659 u8 RAWaitingCounter; 660 u8 RAPendingCounter; 661 u8 PTActive; /* on or off */ 662 u8 PTTryState; /* 0 trying state, 1 for decision state */ 663 u8 PTStage; /* 0~6 */ 664 u8 PTStopCount; /* Stop PT counter */ 665 u8 PTPreRate; /* if rate change do PT */ 666 u8 PTPreRssi; /* if RSSI change 5% do PT */ 667 u8 PTModeSS; /* decide whitch rate should do PT */ 668 u8 RAstage; /* StageRA, decide how many times RA will be done between PT */ 669 u8 PTSmoothFactor; 670 } ODM_RA_INFO_T, *PODM_RA_INFO_T; 671 672 typedef struct _IQK_MATRIX_REGS_SETTING { 673 bool bIQKDone; 674 s32 Value[3][IQK_Matrix_REG_NUM]; 675 bool bBWIqkResultSaved[3]; 676 } IQK_MATRIX_REGS_SETTING, *PIQK_MATRIX_REGS_SETTING; 677 678 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */ 679 680 typedef struct ODM_RF_Calibration_Structure { 681 /* for tx power tracking */ 682 683 u32 RegA24; /* for TempCCK */ 684 s32 RegE94; 685 s32 RegE9C; 686 s32 RegEB4; 687 s32 RegEBC; 688 689 u8 TXPowercount; 690 bool bTXPowerTrackingInit; 691 bool bTXPowerTracking; 692 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 693 u8 TM_Trigger; 694 u8 InternalPA5G[2]; /* pathA / pathB */ 695 696 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 697 u8 ThermalValue; 698 u8 ThermalValue_LCK; 699 u8 ThermalValue_IQK; 700 u8 ThermalValue_DPK; 701 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 702 u8 ThermalValue_AVG_index; 703 u8 ThermalValue_RxGain; 704 u8 ThermalValue_Crystal; 705 u8 ThermalValue_DPKstore; 706 u8 ThermalValue_DPKtrack; 707 bool TxPowerTrackingInProgress; 708 709 bool bReloadtxpowerindex; 710 u8 bRfPiEnable; 711 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 712 713 /* Tx power Tracking ------------------------- */ 714 u8 bCCKinCH14; 715 u8 CCK_index; 716 u8 OFDM_index[MAX_RF_PATH]; 717 s8 PowerIndexOffset[MAX_RF_PATH]; 718 s8 DeltaPowerIndex[MAX_RF_PATH]; 719 s8 DeltaPowerIndexLast[MAX_RF_PATH]; 720 bool bTxPowerChanged; 721 722 u8 ThermalValue_HP[HP_THERMAL_NUM]; 723 u8 ThermalValue_HP_index; 724 IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 725 bool bNeedIQK; 726 bool bIQKInProgress; 727 u8 Delta_IQK; 728 u8 Delta_LCK; 729 s8 BBSwingDiff2G, BBSwingDiff5G; /* Unit: dB */ 730 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; 731 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; 732 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; 733 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; 734 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; 735 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; 736 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; 737 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; 738 u8 DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 739 u8 DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 740 u8 DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 741 u8 DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 742 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; 743 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; 744 745 /* */ 746 747 /* for IQK */ 748 u32 RegC04; 749 u32 Reg874; 750 u32 RegC08; 751 u32 RegB68; 752 u32 RegB6C; 753 u32 Reg870; 754 u32 Reg860; 755 u32 Reg864; 756 757 bool bIQKInitialized; 758 bool bLCKInProgress; 759 bool bAntennaDetected; 760 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 761 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 762 u32 IQK_BB_backup_recover[9]; 763 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 764 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ 765 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ 766 767 /* for APK */ 768 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 769 u8 bAPKdone; 770 u8 bAPKThermalMeterIgnore; 771 772 /* DPK */ 773 bool bDPKFail; 774 u8 bDPdone; 775 u8 bDPPathAOK; 776 u8 bDPPathBOK; 777 778 u32 TxLOK[2]; 779 780 } ODM_RF_CAL_T, *PODM_RF_CAL_T; 781 /* */ 782 /* ODM Dynamic common info value definition */ 783 /* */ 784 785 typedef struct _FAST_ANTENNA_TRAINNING_ { 786 u8 Bssid[6]; 787 u8 antsel_rx_keep_0; 788 u8 antsel_rx_keep_1; 789 u8 antsel_rx_keep_2; 790 u8 antsel_rx_keep_3; 791 u32 antSumRSSI[7]; 792 u32 antRSSIcnt[7]; 793 u32 antAveRSSI[7]; 794 u8 FAT_State; 795 u32 TrainIdx; 796 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 797 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 798 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 799 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 800 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 801 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 802 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 803 u8 RxIdleAnt; 804 bool bBecomeLinked; 805 u32 MinMaxRSSI; 806 u8 idx_AntDiv_counter_2G; 807 u8 idx_AntDiv_counter_5G; 808 u32 AntDiv_2G_5G; 809 u32 CCK_counter_main; 810 u32 CCK_counter_aux; 811 u32 OFDM_counter_main; 812 u32 OFDM_counter_aux; 813 814 u32 CCK_CtrlFrame_Cnt_main; 815 u32 CCK_CtrlFrame_Cnt_aux; 816 u32 OFDM_CtrlFrame_Cnt_main; 817 u32 OFDM_CtrlFrame_Cnt_aux; 818 u32 MainAnt_CtrlFrame_Sum; 819 u32 AuxAnt_CtrlFrame_Sum; 820 u32 MainAnt_CtrlFrame_Cnt; 821 u32 AuxAnt_CtrlFrame_Cnt; 822 823 } FAT_T, *pFAT_T; 824 825 typedef enum _FAT_STATE { 826 FAT_NORMAL_STATE = 0, 827 FAT_TRAINING_STATE = 1, 828 } FAT_STATE_E, *PFAT_STATE_E; 829 830 typedef enum _ANT_DIV_TYPE { 831 NO_ANTDIV = 0xFF, 832 CG_TRX_HW_ANTDIV = 0x01, 833 CGCS_RX_HW_ANTDIV = 0x02, 834 FIXED_HW_ANTDIV = 0x03, 835 CG_TRX_SMART_ANTDIV = 0x04, 836 CGCS_RX_SW_ANTDIV = 0x05, 837 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */ 838 } ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; 839 840 typedef struct _ODM_PATH_DIVERSITY_ { 841 u8 RespTxPath; 842 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM]; 843 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 844 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 845 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 846 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 847 } PATHDIV_T, *pPATHDIV_T; 848 849 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE { 850 PHY_REG_PG_RELATIVE_VALUE = 0, 851 PHY_REG_PG_EXACT_VALUE = 1 852 } PHY_REG_PG_TYPE; 853 854 /* */ 855 /* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */ 856 /* */ 857 typedef struct _ANT_DETECTED_INFO { 858 bool bAntDetected; 859 u32 dBForAntA; 860 u32 dBForAntB; 861 u32 dBForAntO; 862 } ANT_DETECTED_INFO, *PANT_DETECTED_INFO; 863 864 /* */ 865 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 866 /* */ 867 typedef struct DM_Out_Source_Dynamic_Mechanism_Structure { 868 /* RT_TIMER FastAntTrainingTimer; */ 869 /* */ 870 /* Add for different team use temporarily */ 871 /* */ 872 struct adapter *Adapter; /* For CE/NIC team */ 873 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ 874 bool odm_ready; 875 876 PHY_REG_PG_TYPE PhyRegPgValueType; 877 u8 PhyRegPgVersion; 878 879 u64 DebugComponents; 880 u32 DebugLevel; 881 882 u32 NumQryPhyStatusAll; /* CCK + OFDM */ 883 u32 LastNumQryPhyStatusAll; 884 u32 RxPWDBAve; 885 bool MPDIG_2G; /* off MPDIG */ 886 u8 Times_2G; 887 888 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 889 bool bCckHighPower; 890 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 891 u8 ControlChannel; 892 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 893 894 /* REMOVED COMMON INFO---------- */ 895 /* u8 PseudoMacPhyMode; */ 896 /* bool *BTCoexist; */ 897 /* bool PseudoBtCoexist; */ 898 /* u8 OPMode; */ 899 /* bool bAPMode; */ 900 /* bool bClientMode; */ 901 /* bool bAdHocMode; */ 902 /* bool bSlaveOfDMSP; */ 903 /* REMOVED COMMON INFO---------- */ 904 905 /* 1 COMMON INFORMATION */ 906 907 /* */ 908 /* Init Value */ 909 /* */ 910 /* HOOK BEFORE REG INIT----------- */ 911 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ 912 u8 SupportPlatform; 913 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */ 914 u32 SupportAbility; 915 /* ODM PCIE/USB/SDIO = 1/2/3 */ 916 u8 SupportInterface; 917 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 918 u32 SupportICType; 919 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 920 u8 CutVersion; 921 /* Fab Version TSMC/UMC = 0/1 */ 922 u8 FabVersion; 923 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 924 u8 RFType; 925 u8 RFEType; 926 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 927 u8 BoardType; 928 u8 PackageType; 929 u8 TypeGLNA; 930 u8 TypeGPA; 931 u8 TypeALNA; 932 u8 TypeAPA; 933 /* with external LNA NO/Yes = 0/1 */ 934 u8 ExtLNA; 935 u8 ExtLNA5G; 936 /* with external PA NO/Yes = 0/1 */ 937 u8 ExtPA; 938 u8 ExtPA5G; 939 /* with external TRSW NO/Yes = 0/1 */ 940 u8 ExtTRSW; 941 u8 PatchID; /* Customer ID */ 942 bool bInHctTest; 943 bool bWIFITest; 944 945 bool bDualMacSmartConcurrent; 946 u32 BK_SupportAbility; 947 u8 AntDivType; 948 /* HOOK BEFORE REG INIT----------- */ 949 950 /* */ 951 /* Dynamic Value */ 952 /* */ 953 /* POINTER REFERENCE----------- */ 954 955 u8 u8_temp; 956 bool bool_temp; 957 struct adapter *adapter_temp; 958 959 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 960 u8 *pMacPhyMode; 961 /* TX Unicast byte count */ 962 u64 *pNumTxBytesUnicast; 963 /* RX Unicast byte count */ 964 u64 *pNumRxBytesUnicast; 965 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 966 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */ 967 /* Frequence band 2.4G/5G = 0/1 */ 968 u8 *pBandType; 969 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 970 u8 *pSecChOffset; 971 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 972 u8 *pSecurity; 973 /* BW info 20M/40M/80M = 0/1/2 */ 974 u8 *pBandWidth; 975 /* Central channel location Ch1/Ch2/.... */ 976 u8 *pChannel; /* central channel number */ 977 bool DPK_Done; 978 /* Common info for 92D DMSP */ 979 980 bool *pbGetValueFromOtherMac; 981 struct adapter **pBuddyAdapter; 982 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 983 /* Common info for Status */ 984 bool *pbScanInProcess; 985 bool *pbPowerSaving; 986 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 987 u8 *pOnePathCCA; 988 /* pMgntInfo->AntennaTest */ 989 u8 *pAntennaTest; 990 bool *pbNet_closed; 991 u8 *mp_mode; 992 /* u8 *pAidMap; */ 993 u8 *pu1ForcedIgiLb; 994 /* For 8723B IQK----------- */ 995 bool *pIs1Antenna; 996 u8 *pRFDefaultPath; 997 /* 0:S1, 1:S0 */ 998 999 /* POINTER REFERENCE----------- */ 1000 u16 *pForcedDataRate; 1001 /* CALL BY VALUE------------- */ 1002 bool bLinkInProcess; 1003 bool bWIFI_Direct; 1004 bool bWIFI_Display; 1005 bool bLinked; 1006 1007 bool bsta_state; 1008 u8 RSSI_Min; 1009 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 1010 bool bIsMPChip; 1011 bool bOneEntryOnly; 1012 /* Common info for BTDM */ 1013 bool bBtEnabled; /* BT is disabled */ 1014 bool bBtConnectProcess; /* BT HS is under connection progress. */ 1015 u8 btHsRssi; /* BT HS mode wifi rssi value. */ 1016 bool bBtHsOperation; /* BT HS mode is under progress */ 1017 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 1018 bool bBtLimitedDig; /* BT is busy. */ 1019 /* CALL BY VALUE------------- */ 1020 u8 RSSI_A; 1021 u8 RSSI_B; 1022 u64 RSSI_TRSW; 1023 u64 RSSI_TRSW_H; 1024 u64 RSSI_TRSW_L; 1025 u64 RSSI_TRSW_iso; 1026 1027 u8 RxRate; 1028 bool bNoisyState; 1029 u8 TxRate; 1030 u8 LinkedInterval; 1031 u8 preChannel; 1032 u32 TxagcOffsetValueA; 1033 bool IsTxagcOffsetPositiveA; 1034 u32 TxagcOffsetValueB; 1035 bool IsTxagcOffsetPositiveB; 1036 u64 lastTxOkCnt; 1037 u64 lastRxOkCnt; 1038 u32 BbSwingOffsetA; 1039 bool IsBbSwingOffsetPositiveA; 1040 u32 BbSwingOffsetB; 1041 bool IsBbSwingOffsetPositiveB; 1042 s8 TH_L2H_ini; 1043 s8 TH_EDCCA_HL_diff; 1044 s8 IGI_Base; 1045 u8 IGI_target; 1046 bool ForceEDCCA; 1047 u8 AdapEn_RSSI; 1048 s8 Force_TH_H; 1049 s8 Force_TH_L; 1050 u8 IGI_LowerBound; 1051 u8 antdiv_rssi; 1052 u8 AntType; 1053 u8 pre_AntType; 1054 u8 antdiv_period; 1055 u8 antdiv_select; 1056 u8 NdpaPeriod; 1057 bool H2C_RARpt_connect; 1058 1059 /* add by Yu Cehn for adaptivtiy */ 1060 bool adaptivity_flag; 1061 bool NHM_disable; 1062 bool TxHangFlg; 1063 bool Carrier_Sense_enable; 1064 u8 tolerance_cnt; 1065 u64 NHMCurTxOkcnt; 1066 u64 NHMCurRxOkcnt; 1067 u64 NHMLastTxOkcnt; 1068 u64 NHMLastRxOkcnt; 1069 u8 txEdcca1; 1070 u8 txEdcca0; 1071 s8 H2L_lb; 1072 s8 L2H_lb; 1073 u8 Adaptivity_IGI_upper; 1074 u8 NHM_cnt_0; 1075 1076 ODM_NOISE_MONITOR noise_level;/* ODM_MAX_CHANNEL_NUM]; */ 1077 /* */ 1078 /* 2 Define STA info. */ 1079 /* _ODM_STA_INFO */ 1080 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 1081 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 1082 1083 /* */ 1084 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 1085 /* We need to colelct all support abilit to a proper area. */ 1086 /* */ 1087 bool RaSupport88E; 1088 1089 /* Define ........... */ 1090 1091 /* Latest packet phy info (ODM write) */ 1092 struct odm_phy_dbg_info PhyDbgInfo; 1093 /* PHY_INFO_88E PhyInfo; */ 1094 1095 /* Latest packet phy info (ODM write) */ 1096 struct odm_mac_status_info *pMacInfo; 1097 /* MAC_INFO_88E MacInfo; */ 1098 1099 /* Different Team independt structure?? */ 1100 1101 /* */ 1102 /* TX_RTP_CMN TX_retrpo; */ 1103 /* TX_RTP_88E TX_retrpo; */ 1104 /* TX_RTP_8195 TX_retrpo; */ 1105 1106 /* */ 1107 /* ODM Structure */ 1108 /* */ 1109 FAT_T DM_FatTable; 1110 DIG_T DM_DigTable; 1111 PS_T DM_PSTable; 1112 struct dynamic_primary_CCA DM_PriCCA; 1113 RXHP_T DM_RXHP_Table; 1114 RA_T DM_RA_Table; 1115 false_ALARM_STATISTICS FalseAlmCnt; 1116 false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 1117 SWAT_T DM_SWAT_Table; 1118 bool RSSI_test; 1119 CFO_TRACKING DM_CfoTrack; 1120 1121 EDCA_T DM_EDCA_Table; 1122 u32 WMMEDCA_BE; 1123 PATHDIV_T DM_PathDiv; 1124 /* Copy from SD4 structure */ 1125 /* */ 1126 /* ================================================== */ 1127 /* */ 1128 1129 /* common */ 1130 /* u8 DM_Type; */ 1131 /* u8 PSD_Report_RXHP[80]; Add By Gary */ 1132 /* u8 PSD_func_flag; Add By Gary */ 1133 /* for DIG */ 1134 /* u8 bDMInitialGainEnable; */ 1135 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */ 1136 /* for Antenna diversity */ 1137 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */ 1138 /* PSTA_INFO_T RSSI_target; */ 1139 1140 bool *pbDriverStopped; 1141 bool *pbDriverIsGoingToPnpSetPowerSleep; 1142 bool *pinit_adpt_in_progress; 1143 1144 /* PSD */ 1145 bool bUserAssignLevel; 1146 RT_TIMER PSDTimer; 1147 u8 RSSI_BT; /* come from BT */ 1148 bool bPSDinProcess; 1149 bool bPSDactive; 1150 bool bDMInitialGainEnable; 1151 1152 /* MPT DIG */ 1153 RT_TIMER MPT_DIGTimer; 1154 1155 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 1156 u8 bUseRAMask; 1157 1158 ODM_RATE_ADAPTIVE RateAdaptive; 1159 1160 ANT_DETECTED_INFO AntDetectedInfo; /* Antenna detected information for RSSI tool */ 1161 1162 ODM_RF_CAL_T RFCalibrateInfo; 1163 1164 /* */ 1165 /* TX power tracking */ 1166 /* */ 1167 u8 BbSwingIdxOfdm[MAX_RF_PATH]; 1168 u8 BbSwingIdxOfdmCurrent; 1169 u8 BbSwingIdxOfdmBase[MAX_RF_PATH]; 1170 bool BbSwingFlagOfdm; 1171 u8 BbSwingIdxCck; 1172 u8 BbSwingIdxCckCurrent; 1173 u8 BbSwingIdxCckBase; 1174 u8 DefaultOfdmIndex; 1175 u8 DefaultCckIndex; 1176 bool BbSwingFlagCck; 1177 1178 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH]; 1179 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH]; 1180 s8 Remnant_CCKSwingIdx; 1181 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */ 1182 bool Modify_TxAGC_Flag_PathA; 1183 bool Modify_TxAGC_Flag_PathB; 1184 bool Modify_TxAGC_Flag_PathC; 1185 bool Modify_TxAGC_Flag_PathD; 1186 bool Modify_TxAGC_Flag_PathA_CCK; 1187 1188 s8 KfreeOffset[MAX_RF_PATH]; 1189 /* */ 1190 /* ODM system resource. */ 1191 /* */ 1192 1193 /* ODM relative time. */ 1194 RT_TIMER PathDivSwitchTimer; 1195 /* 2011.09.27 add for Path Diversity */ 1196 RT_TIMER CCKPathDiversityTimer; 1197 RT_TIMER FastAntTrainingTimer; 1198 1199 /* ODM relative workitem. */ 1200 1201 #if (BEAMFORMING_SUPPORT == 1) 1202 RT_BEAMFORMING_INFO BeamformingInfo; 1203 #endif 1204 } DM_ODM_T, *PDM_ODM_T; /* DM_Dynamic_Mechanism_Structure */ 1205 1206 #define ODM_RF_PATH_MAX 2 1207 1208 typedef enum _ODM_RF_RADIO_PATH { 1209 ODM_RF_PATH_A = 0, /* Radio Path A */ 1210 ODM_RF_PATH_B = 1, /* Radio Path B */ 1211 ODM_RF_PATH_C = 2, /* Radio Path C */ 1212 ODM_RF_PATH_D = 3, /* Radio Path D */ 1213 ODM_RF_PATH_AB, 1214 ODM_RF_PATH_AC, 1215 ODM_RF_PATH_AD, 1216 ODM_RF_PATH_BC, 1217 ODM_RF_PATH_BD, 1218 ODM_RF_PATH_CD, 1219 ODM_RF_PATH_ABC, 1220 ODM_RF_PATH_ACD, 1221 ODM_RF_PATH_BCD, 1222 ODM_RF_PATH_ABCD, 1223 /* ODM_RF_PATH_MAX, Max RF number 90 support */ 1224 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; 1225 1226 typedef enum _ODM_RF_CONTENT { 1227 odm_radioa_txt = 0x1000, 1228 odm_radiob_txt = 0x1001, 1229 odm_radioc_txt = 0x1002, 1230 odm_radiod_txt = 0x1003 1231 } ODM_RF_CONTENT; 1232 1233 typedef enum _ODM_BB_Config_Type { 1234 CONFIG_BB_PHY_REG, 1235 CONFIG_BB_AGC_TAB, 1236 CONFIG_BB_AGC_TAB_2G, 1237 CONFIG_BB_AGC_TAB_5G, 1238 CONFIG_BB_PHY_REG_PG, 1239 CONFIG_BB_PHY_REG_MP, 1240 CONFIG_BB_AGC_TAB_DIFF, 1241 } ODM_BB_Config_Type, *PODM_BB_Config_Type; 1242 1243 typedef enum _ODM_RF_Config_Type { 1244 CONFIG_RF_RADIO, 1245 CONFIG_RF_TXPWR_LMT, 1246 } ODM_RF_Config_Type, *PODM_RF_Config_Type; 1247 1248 typedef enum _ODM_FW_Config_Type { 1249 CONFIG_FW_NIC, 1250 CONFIG_FW_NIC_2, 1251 CONFIG_FW_AP, 1252 CONFIG_FW_WoWLAN, 1253 CONFIG_FW_WoWLAN_2, 1254 CONFIG_FW_AP_WoWLAN, 1255 CONFIG_FW_BT, 1256 } ODM_FW_Config_Type; 1257 1258 /* Status code */ 1259 typedef enum _RT_STATUS { 1260 RT_STATUS_SUCCESS, 1261 RT_STATUS_FAILURE, 1262 RT_STATUS_PENDING, 1263 RT_STATUS_RESOURCE, 1264 RT_STATUS_INVALID_CONTEXT, 1265 RT_STATUS_INVALID_PARAMETER, 1266 RT_STATUS_NOT_SUPPORT, 1267 RT_STATUS_OS_API_FAILED, 1268 } RT_STATUS, *PRT_STATUS; 1269 1270 #ifdef REMOVE_PACK 1271 #pragma pack() 1272 #endif 1273 1274 /* include "odm_function.h" */ 1275 1276 /* 3 =========================================================== */ 1277 /* 3 DIG */ 1278 /* 3 =========================================================== */ 1279 1280 /* Remove DIG by Yuchen */ 1281 1282 /* 3 =========================================================== */ 1283 /* 3 AGC RX High Power Mode */ 1284 /* 3 =========================================================== */ 1285 #define LNA_Low_Gain_1 0x64 1286 #define LNA_Low_Gain_2 0x5A 1287 #define LNA_Low_Gain_3 0x58 1288 1289 #define FA_RXHP_TH1 5000 1290 #define FA_RXHP_TH2 1500 1291 #define FA_RXHP_TH3 800 1292 #define FA_RXHP_TH4 600 1293 #define FA_RXHP_TH5 500 1294 1295 /* 3 =========================================================== */ 1296 /* 3 EDCA */ 1297 /* 3 =========================================================== */ 1298 1299 /* 3 =========================================================== */ 1300 /* 3 Dynamic Tx Power */ 1301 /* 3 =========================================================== */ 1302 /* Dynamic Tx Power Control Threshold */ 1303 1304 /* 3 =========================================================== */ 1305 /* 3 Rate Adaptive */ 1306 /* 3 =========================================================== */ 1307 #define DM_RATR_STA_INIT 0 1308 #define DM_RATR_STA_HIGH 1 1309 #define DM_RATR_STA_MIDDLE 2 1310 #define DM_RATR_STA_LOW 3 1311 1312 /* 3 =========================================================== */ 1313 /* 3 BB Power Save */ 1314 /* 3 =========================================================== */ 1315 1316 typedef enum tag_1R_CCA_Type_Definition { 1317 CCA_1R = 0, 1318 CCA_2R = 1, 1319 CCA_MAX = 2, 1320 } DM_1R_CCA_E; 1321 1322 typedef enum tag_RF_Type_Definition { 1323 RF_Save = 0, 1324 RF_Normal = 1, 1325 RF_MAX = 2, 1326 } DM_RF_E; 1327 1328 /* 3 =========================================================== */ 1329 /* 3 Antenna Diversity */ 1330 /* 3 =========================================================== */ 1331 typedef enum tag_SW_Antenna_Switch_Definition { 1332 Antenna_A = 1, 1333 Antenna_B = 2, 1334 Antenna_MAX = 3, 1335 } DM_SWAS_E; 1336 1337 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 1338 #define MAX_ANTENNA_DETECTION_CNT 10 1339 1340 /* */ 1341 /* Extern Global Variables. */ 1342 /* */ 1343 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE]; 1344 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; 1345 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8]; 1346 1347 extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE]; 1348 extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; 1349 extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]; 1350 1351 extern u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; 1352 1353 /* */ 1354 /* check Sta pointer valid or not */ 1355 /* */ 1356 #define IS_STA_VALID(pSta) (pSta) 1357 /* 20100514 Joseph: Add definition for antenna switching test after link. */ 1358 /* This indicates two different the steps. */ 1359 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1360 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1361 /* with original RSSI to determine if it is necessary to switch antenna. */ 1362 #define SWAW_STEP_PEAK 0 1363 #define SWAW_STEP_DETERMINE 1 1364 1365 /* Remove BB power saving by Yuchen */ 1366 1367 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck 1368 void ODM_TXPowerTrackingCheck(PDM_ODM_T pDM_Odm); 1369 1370 bool ODM_RAStateCheck( 1371 PDM_ODM_T pDM_Odm, 1372 s32 RSSI, 1373 bool bForceUpdate, 1374 u8 *pRATRState 1375 ); 1376 1377 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1378 void ODM_SwAntDivChkPerPktRssi( 1379 PDM_ODM_T pDM_Odm, 1380 u8 StationID, 1381 struct odm_phy_info *pPhyInfo 1382 ); 1383 1384 u32 ODM_Get_Rate_Bitmap( 1385 PDM_ODM_T pDM_Odm, 1386 u32 macid, 1387 u32 ra_mask, 1388 u8 rssi_level 1389 ); 1390 1391 #if (BEAMFORMING_SUPPORT == 1) 1392 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId); 1393 #endif 1394 1395 void odm_TXPowerTrackingInit(PDM_ODM_T pDM_Odm); 1396 1397 void ODM_DMInit(PDM_ODM_T pDM_Odm); 1398 1399 void ODM_DMWatchdog(PDM_ODM_T pDM_Odm); /* For common use in the future */ 1400 1401 void ODM_CmnInfoInit(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, u32 Value); 1402 1403 void ODM_CmnInfoHook(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, void *pValue); 1404 1405 void ODM_CmnInfoPtrArrayHook( 1406 PDM_ODM_T pDM_Odm, 1407 ODM_CMNINFO_E CmnInfo, 1408 u16 Index, 1409 void *pValue 1410 ); 1411 1412 void ODM_CmnInfoUpdate(PDM_ODM_T pDM_Odm, u32 CmnInfo, u64 Value); 1413 1414 void ODM_InitAllTimers(PDM_ODM_T pDM_Odm); 1415 1416 void ODM_CancelAllTimers(PDM_ODM_T pDM_Odm); 1417 1418 void ODM_ReleaseAllTimers(PDM_ODM_T pDM_Odm); 1419 1420 void ODM_AntselStatistics_88C( 1421 PDM_ODM_T pDM_Odm, 1422 u8 MacId, 1423 u32 PWDBAll, 1424 bool isCCKrate 1425 ); 1426 1427 void ODM_DynamicARFBSelect(PDM_ODM_T pDM_Odm, u8 rate, bool Collision_State); 1428 1429 #endif 1430