1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_LINK_SERVICE_TYPES_H__ 27 #define __DAL_LINK_SERVICE_TYPES_H__ 28 29 #include "grph_object_id.h" 30 #include "dal_types.h" 31 #include "irq_types.h" 32 33 /*struct mst_mgr_callback_object;*/ 34 struct ddc; 35 struct irq_manager; 36 37 enum { 38 MAX_CONTROLLER_NUM = 6 39 }; 40 41 enum dp_power_state { 42 DP_POWER_STATE_D0 = 1, 43 DP_POWER_STATE_D3 44 }; 45 46 enum edp_revision { 47 /* eDP version 1.1 or lower */ 48 EDP_REVISION_11 = 0x00, 49 /* eDP version 1.2 */ 50 EDP_REVISION_12 = 0x01, 51 /* eDP version 1.3 */ 52 EDP_REVISION_13 = 0x02 53 }; 54 55 enum { 56 LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/ 57 }; 58 59 enum link_training_result { 60 LINK_TRAINING_SUCCESS, 61 LINK_TRAINING_CR_FAIL_LANE0, 62 LINK_TRAINING_CR_FAIL_LANE1, 63 LINK_TRAINING_CR_FAIL_LANE23, 64 /* CR DONE bit is cleared during EQ step */ 65 LINK_TRAINING_EQ_FAIL_CR, 66 /* other failure during EQ step */ 67 LINK_TRAINING_EQ_FAIL_EQ, 68 LINK_TRAINING_LQA_FAIL, 69 /* one of the CR,EQ or symbol lock is dropped */ 70 LINK_TRAINING_LINK_LOSS, 71 }; 72 73 struct link_training_settings { 74 struct dc_link_settings link_settings; 75 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; 76 77 enum dc_voltage_swing *voltage_swing; 78 enum dc_pre_emphasis *pre_emphasis; 79 enum dc_post_cursor2 *post_cursor2; 80 81 uint16_t cr_pattern_time; 82 uint16_t eq_pattern_time; 83 enum dc_dp_training_pattern pattern_for_cr; 84 enum dc_dp_training_pattern pattern_for_eq; 85 86 bool enhanced_framing; 87 bool allow_invalid_msa_timing_param; 88 }; 89 90 /*TODO: Move this enum test harness*/ 91 /* Test patterns*/ 92 enum dp_test_pattern { 93 /* Input data is pass through Scrambler 94 * and 8b10b Encoder straight to output*/ 95 DP_TEST_PATTERN_VIDEO_MODE = 0, 96 97 /* phy test patterns*/ 98 DP_TEST_PATTERN_PHY_PATTERN_BEGIN, 99 DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN, 100 DP_TEST_PATTERN_SYMBOL_ERROR, 101 DP_TEST_PATTERN_PRBS7, 102 DP_TEST_PATTERN_80BIT_CUSTOM, 103 DP_TEST_PATTERN_CP2520_1, 104 DP_TEST_PATTERN_CP2520_2, 105 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2, 106 DP_TEST_PATTERN_CP2520_3, 107 108 /* Link Training Patterns */ 109 DP_TEST_PATTERN_TRAINING_PATTERN1, 110 DP_TEST_PATTERN_TRAINING_PATTERN2, 111 DP_TEST_PATTERN_TRAINING_PATTERN3, 112 DP_TEST_PATTERN_TRAINING_PATTERN4, 113 DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4, 114 115 /* link test patterns*/ 116 DP_TEST_PATTERN_COLOR_SQUARES, 117 DP_TEST_PATTERN_COLOR_SQUARES_CEA, 118 DP_TEST_PATTERN_VERTICAL_BARS, 119 DP_TEST_PATTERN_HORIZONTAL_BARS, 120 DP_TEST_PATTERN_COLOR_RAMP, 121 122 /* audio test patterns*/ 123 DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED, 124 DP_TEST_PATTERN_AUDIO_SAWTOOTH, 125 126 DP_TEST_PATTERN_UNSUPPORTED 127 }; 128 129 enum dp_test_pattern_color_space { 130 DP_TEST_PATTERN_COLOR_SPACE_RGB, 131 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601, 132 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709, 133 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED 134 }; 135 136 enum dp_panel_mode { 137 /* not required */ 138 DP_PANEL_MODE_DEFAULT, 139 /* standard mode for eDP */ 140 DP_PANEL_MODE_EDP, 141 /* external chips specific settings */ 142 DP_PANEL_MODE_SPECIAL 143 }; 144 145 /* DPCD_ADDR_TRAINING_LANEx_SET registers value */ 146 union dpcd_training_lane_set { 147 struct { 148 #if defined(LITTLEENDIAN_CPU) 149 uint8_t VOLTAGE_SWING_SET:2; 150 uint8_t MAX_SWING_REACHED:1; 151 uint8_t PRE_EMPHASIS_SET:2; 152 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 153 /* following is reserved in DP 1.1 */ 154 uint8_t POST_CURSOR2_SET:2; 155 #elif defined(BIGENDIAN_CPU) 156 uint8_t POST_CURSOR2_SET:2; 157 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 158 uint8_t PRE_EMPHASIS_SET:2; 159 uint8_t MAX_SWING_REACHED:1; 160 uint8_t VOLTAGE_SWING_SET:2; 161 #else 162 #error ARCH not defined! 163 #endif 164 } bits; 165 166 uint8_t raw; 167 }; 168 169 170 /* DP MST stream allocation (payload bandwidth number) */ 171 struct dp_mst_stream_allocation { 172 uint8_t vcp_id; 173 /* number of slots required for the DP stream in 174 * transport packet */ 175 uint8_t slot_count; 176 }; 177 178 /* DP MST stream allocation table */ 179 struct dp_mst_stream_allocation_table { 180 /* number of DP video streams */ 181 int stream_count; 182 /* array of stream allocations */ 183 struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 184 }; 185 186 #endif /*__DAL_LINK_SERVICE_TYPES_H__*/ 187